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Cannot find function "TO_INTEGER" for these actuals

 
 
Travis
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      06-15-2013
Hi all, I'm compiling the following VHDL to make a simple ROM, and I'm getting these errors:
# Error: COMP96_0305: SUBONE_MODULE_VHDL.vhd : (93, 23): Cannot find function "TO_INTEGER" for these actuals.
# Error: COMP96_0138: SUBONE_MODULE_VHDL.vhd : (93, 23): The index types in the reference to the array object are incompatible with its range type.

I'm using Active-HDL 9.2. This was based off an example I got online, but I had to switch to the NUMERIC_STD IEEE library because I want to synthesize this.

Thanks!

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;


entity SUBONE_MODULE_VHDL is
port(
addr : in STD_LOGIC_VECTOR(4 downto 0);
clk : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(4 downto 0)
);
end SUBONE_MODULE_VHDL;

--}} End of automatically maintained section

architecture SUBONE_MODULE_VHDL of SUBONE_MODULE_VHDL is

-- enter your statements here --

type ROM_Array is array (0 to 31)
of std_logic_vector(4 downto 0);


constant Content: ROM_Array := (
0 => "10011", -- Suppose ROM has
1 => "00000", -- prestored value
2 => "00001", -- like this table
3 => "00010", --
4 => "00011", --
5 => "00100", --
6 => "00101", --
7 => "00110", --
8 => "00111", --
9 => "01000", --
10 => "01001", --
11 => "01010", --
12 => "01011", --
13 => "01100", --
14 => "01101", --
15 => "01110", --
16 => "01111", --
17 => "01110", --
18 => "01110", --
19 => "01110", --
20 => "01110", --
21 => "00000", --
22 => "00001", --
23 => "00010", --
24 => "00011", --
25 => "00100", --
26 => "00101", --
27 => "00110", --
28 => "00111", --
29 => "01000", --
30 => "01001", --
31 => "01010", --
OTHERS => "00000"
);

begin
process(clk, addr)
variable addr : integer := 0;
begin
if( clk'event and clk = '1' ) then
dout <= Content(TO_INTEGER(addr));
end if;
end process;


end SUBONE_MODULE_VHDL;
 
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KJ
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      06-15-2013
You have...

dout <= Content(TO_INTEGER(addr));

should be...

dout <= Content(TO_INTEGER(unsigned(addr)));

The reason is that addr is defined to be a std_logic_vector. Std_logic_vector has no numeric interpretation it is just an arbitrary collection of bits. By casting it as 'unsigned' you are saying to interpret it as an unsigned numeric quantity which can then be converted to an integer value.

Kevin Jennings
 
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Travis
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      06-15-2013
Thank you so much! I'll try it ASAP and report back!

On Friday, June 14, 2013 7:47:28 PM UTC-7, KJ wrote:
> You have...
>
>
>
> dout <= Content(TO_INTEGER(addr));
>
>
>
> should be...
>
>
>
> dout <= Content(TO_INTEGER(unsigned(addr)));
>
>
>
> The reason is that addr is defined to be a std_logic_vector. Std_logic_vector has no numeric interpretation it is just an arbitrary collection of bits. By casting it as 'unsigned' you are saying to interpret it as an unsigned numeric quantity which can then be converted to an integer value.
>
>
>
> Kevin Jennings


 
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Andy
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      06-17-2013
Travis,

You also need to remove the unused variable declaration for addr in the process. It is hiding the addr port.

Andy
 
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Travis
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      06-17-2013
Hi Andy,

I just tried Kevin's solution, noticed the error, got bummed, noticed your solution, and now all is fixed. Thank you both!

Andy & Kevin, if I could ask, it appears I was interpreting what "variable addr : integer;" was doing. I thought it was providing context for use of "addr" within the process block, but this is apparently incorrect. Do you have a good reference or pointer for these types of things?

Thanks again!

On Monday, June 17, 2013 5:57:45 AM UTC-7, Andy wrote:
> Travis,
>
>
>
> You also need to remove the unused variable declaration for addr in the process. It is hiding the addr port.
>
>
>
> Andy


 
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kevin.neilson@xilinx.com
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      06-17-2013
Another option is to make the input 'unsigned', which is a better type in this context.
 
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Andy
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      06-17-2013
Variables are storage objects that are usually local to processes or subprograms where they are declared. They are assigned using ":=" instead of "<=". Their value updates immediately upon execution of the assignment statement, instead of waiting until the process suspends, like signal values do.

Most VHDL texts cover variables, but most will tell you not to use them forRTL (or at least not for registers in RTL), which is unfortunate, since variables are quite powerful for both combinatorial and register logic, once you know how to use them.

Andy
 
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Andy
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      06-17-2013
What Kevin said (make addr unsigned).

Or, if your tools support vhdl-2008, you can use the new package ieee.numeric_std_unsigned.all, and use to_integer(addr) without converting (or changing) addr to unsigned.

Andy
 
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Travis
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      06-18-2013
Xilinx ISE won't be supporting VHDL 2008 at all, apparently they're reserving that for the Vivado tools, which is truly sad because it looks like VHDL2008 is a meaningful update.

On Monday, June 17, 2013 10:28:03 AM UTC-7, Andy wrote:
> What Kevin said (make addr unsigned).
>
>
>
> Or, if your tools support vhdl-2008, you can use the new package ieee.numeric_std_unsigned.all, and use to_integer(addr) without converting (or changing) addr to unsigned.
>
>
>
> Andy


 
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kevin.neilson@xilinx.com
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      06-18-2013
And who knows how much 2008 Vivado really supports. Probably not much. Use Synplify, if possible. The VHDL 2008 additions are indispensable. One thing I could not do without is the fixed-point package.
 
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