Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > DSP48 in synchronous process or not, what's the difference?

Reply
Thread Tools

DSP48 in synchronous process or not, what's the difference?

 
 
Ethan Zheng
Guest
Posts: n/a
 
      06-10-2013
I am so curious about the behavior difference between the following codes.
Please comment,

CODE1:
signal reg_in : signed(17 downto 0);
signal reg_product : signal(35 downto 0);

Product_out_pipe_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEM
reg_in <= port_in; -- multiplication pipeline in
reg_product <= reg_in * reg_in; -- pipeline out
port_out <= reg_product;
END IF;
END PROCESS Product_out_pipe_process;

CODE2:
signal reg_in : signed(17 downto 0);
signal reg_product : signal(35 downto 0);
signal reg_product_1 : signal(35 downto 0);

Pipe_in_process : PROGRESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEM
reg_in <= port_in;
END IF
END PROCESS Pipe_in_process;

reg_product <= reg_in * reg_in; -- multiplication not clk sensitive

Pipe_out_process : PROGRESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEM
reg_product_1 <= reg_product
END IF
END PROGRESS Pipe_out_process


 
Reply With Quote
 
 
 
 
Andy
Guest
Posts: n/a
 
      06-10-2013
In code2, reg_product is not a register, so it does not consume a clock cycle, but it does consume one in code1.

Andy
 
Reply With Quote
 
 
 
 
goouse99@gmail.com
Guest
Posts: n/a
 
      06-12-2013
Am Montag, 10. Juni 2013 21:08:15 UTC+2 schrieb Ethan Zheng:
> I am so curious about the behavior difference between the following codes.
>
> Please comment,
>
>
>
> CODE1:
>
> signal reg_in : signed(17 downto 0);
>
> signal reg_product : signal(35 downto 0);
>
>
>
> Product_out_pipe_process : PROCESS (clk)
>
> BEGIN
>
> IF clk'EVENT AND clk = '1' THEM
>
> reg_in <= port_in; -- multiplication pipeline in
>
> reg_product <= reg_in * reg_in; -- pipeline out
>
> port_out <= reg_product;
>
> END IF;
>
> END PROCESS Product_out_pipe_process;
>
>
>
> CODE2:
>
> signal reg_in : signed(17 downto 0);
>
> signal reg_product : signal(35 downto 0);
>
> signal reg_product_1 : signal(35 downto 0);
>
>
>
> Pipe_in_process : PROGRESS (clk)
>
> BEGIN
>
> IF clk'EVENT AND clk = '1' THEM
>
> reg_in <= port_in;
>
> END IF
>
> END PROCESS Pipe_in_process;
>
>
>
> reg_product <= reg_in * reg_in; -- multiplication not clk sensitive
>
>
>
> Pipe_out_process : PROGRESS (clk)
>
> BEGIN
>
> IF clk'EVENT AND clk = '1' THEM
>
> reg_product_1 <= reg_product
>
> END IF
>
> END PROGRESS Pipe_out_process


Hi,
Code1 has a latency of 3 while code 2 has a latency of 2.
(I assume reg_product1 to be identical with port_out).

Code 2 could be rewritten like this without functional changes:
Pipe_out_process : PROGRESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEM
reg_product_1 <= reg_in*reg_in; -- now inside sync process,
END IF
END PROGRESS Pipe_out_process

Both architectures might synthesize to DSP48, since the multiplication is enclosed with registers. Additional pipeline stages are possible, but only required if your algorithm needs it. Otherwise you are just wasting clock cycles.

Have a nice synthesis
Eilert
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
What was the project that made you feel skilled in Python? Ned Batchelder Python 2 05-20-2013 03:16 PM
Re: What was the project that made you feel skilled in Python? Chris Angelico Python 0 05-19-2013 11:48 AM
What is the reason for defining classes within classes in Python? vasudevram Python 6 04-24-2013 01:29 PM
what is the advantage of using maven for java standalone app mcheung63@gmail.com Java 13 04-16-2013 01:42 AM



Advertisments