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abstract type signal

 
 
Ilya Kalistru
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      05-22-2013
Hi everyone!

I have a module, that makes some actions with signal S of the type myType. This actions with signal S is independent of its type.

For using this modules for signals of various types I create a copies of module with another name and "Find and replace" myType to MyOtherType.
I think that it is conceptually wrong way.

Is there a way to define a signal of abstract data type and substitute the correct type in place abstract when I need use it? May I use "generic" for this purpose?

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Best Regards,
Ilya Kalistru
Engineer looking for a complicated job.
 
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Rob Gaddi
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      05-22-2013
On Wed, 22 May 2013 12:08:12 -0700 (PDT)
Ilya Kalistru <(E-Mail Removed)> wrote:

> Hi everyone!
>
> I have a module, that makes some actions with signal S of the type myType. This actions with signal S is independent of its type.
>
> For using this modules for signals of various types I create a copies of module with another name and "Find and replace" myType to MyOtherType.
> I think that it is conceptually wrong way.
>
> Is there a way to define a signal of abstract data type and substitute the correct type in place abstract when I need use it? May I use "generic" for this purpose?
>
> --
> Best Regards,
> Ilya Kalistru
> Engineer looking for a complicated job.


That's a feature in VHDL-2008, and in my experience one that's not very widely supported yet.

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Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.
 
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Andy
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      05-23-2013
I agree with Rob, but notify your tool vendor(s) if they do not yet support it(generic types). This will help them prioritize implementation of 2008 features, and let the know that more customers want to use 2008 features.

Andy
 
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kevin.neilson@xilinx.com
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      05-23-2013
I had the same experience recently in which I had to make four almost-identical modules so I tried passing in the type as a generic, which looks like this:

entity delay is
generic (type DATATYPE);
port (...

In my notes I see that this was supported by my synthesizer (Synplify Pro) but not by Modelsim 10.1d, which despite being sold for ridiculous prices, does not support basic features from a standard from 2008, which if I calculate correctly, was FIVE YEARS AGO.

Even if this feature is supported, it's not really that great. It would bepreferable to have an unconstrained type, so you could do something like this:

signal internal_sig : data_in'type(data_in'range);

Your other option is to use Verilog.
 
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