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Counting number of asserted register bits in VHDL

 
 
Andy
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      05-16-2013
Kevin,

Did you try to_integer(unsigned'(0 => mod_cmplt(k)))?

I usually use the if statement anyway. Much more readable.

Verilog: "Hold my beer and watch this!"

Andy
 
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kevin.neilson@xilinx.com
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      05-17-2013
Andy: Yes, that does work, with the unsigned cast (using ') instead of the unsigned function. I don't really know the difference, but the cast does work.
-Kevin
 
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Andy
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      05-17-2013

Kevin, leaving out the ' was an unfortunate typo in my original suggestion.

Unsigned() is a built-in type conversion function from any closely related type to unsigned (a cast). In order for it to work, the argument must be statically determinable to be of a single type that is acceptable for the converion function.

The problem is (0 => [std_logic expression]) could be any of: slv, sulv, signed or unsigned, and perhaps others if additional packages are used. More importantly, all of those potential types are closely related to unsigned and allowable arguments for unsigned(). Thus the compiler cannot make a unique determination of which ONE of those types to use, so it throws an error (even though we know it really would not make a difference in the end).

Unsigned'() is a type designator. The type designator tells the compiler that the following anonymous expression IS of the type indicated. It is used when the following anonymous expression could be numerous types that would all "work", but VHDL needs to know which ONE of those that "will work" it should use.

Hope this helps,

Andy
 
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