Hello,

I have a status register of width, R_SIZE. This is a generic so the register width may be different depending on the application. The R_SIZE is limited to values, 4, 8 and 16.

Each bit in the register is set by different module as an indication of that module's done status. These status bits are asserted for only one clock and may be asserted again as each module may run its application multiple times on different data.

I need to count the number of bits set in the status register on each clock and accumulate a total to match a predetermined "max" value.

I thought I'd use the VHDL 'generate' statement to compile RTL based on R_SIZE as follows.

=================== start RTL =====================

architecture behave of b is

component modx port(

mod_cmplt : out std_logic

);

end component modx;

signal mod_cmplt : std_logic_vector(15 downto 0);

signal cmplt_cnt : integer range 0 to 512;

signal next_cmplt_cnt : integer range 0 to 512;

begin

mod_cmplt(15 downto R_SIZE) <= (others => '0');

g1: for i in 0 to R_SIZE-1 generate

u_modx : modx port map(

mod_cmplt => mod_cmplt(i)

);

end generate;

process (mod_cmplt, cmplt_cnt)

begin

next_cmplt_cnt <= cmplt_cnt;

gen4: if R_SIZE = 4 generate

next_cmplt_cnt <= mod_cmplt(0) + mod_cmplt(1) + mod_cmplt(2) +

mod_cmplt(3) + cmplt_cnt;

end generate;

gen8: if R_SIZE = 8 generate

next_cmplt_cnt <= mod_cmplt(0) + mod_cmplt(1) + mod_cmplt(2) +

mod_cmplt(3) + mod_cmplt(4) + mod_cmplt(5) +

mod_cmplt(6) + mod_cmplt(7) + cmplt_cnt;

end generate;

gen16:if R_SIZE = 16 generate

next_cmplt_cnt <= mod_cmplt(0) + mod_cmplt(1) + mod_cmplt(2) +

mod_cmplt(3) + mod_cmplt(4) + mod_cmplt(5) +

mod_cmplt(6) + mod_cmplt(7) + mod_cmplt(

+

mod_cmplt(9) + mod_cmplt(10) + mod_cmplt(11) +

mod_cmplt(12) + mod_cmplt(13) + mod_cmplt(14) +

mod_cmplt(15) + cmplt_cnt;

end generate

end process;

process (reset, clk)

begin

if (reset = '1') then

cmplt_cnt <= 0;

elsif (clk'event and clk='1')

cmplt_cnt <= next_cmplt_cnt;

end if;

end process

end behave;

================================ end RTL =================

The first error I get is a syntax error:

Error-[IEEEVHDLSYNTAXERR] Syntax error

gen4: if R_SIZE = 4 generate

^

Syntax error detected during VHDL parsing.

I don't know what to do about this. Is there a better way to code what I want the system to do?

Thank you.