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Announcing release of OSVVM 2013.04

Jim Lewis
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OSVVM release 2013.04 is now available at either or

Open Source VHDL Verification Methodology (OSVVM) is VHDLs leading edge verification methodology. OSVVM makes adding functional coverage, randomization, and Intelligent Coverage (coverage driven randomization) to your VHDL testbench simple, concise, and powerful.

With OSVVM, you don't need a specialized verification language such as SystemVerilog or 'e' to do verification, in fact, in many key areas, OSVVM is astep ahead.

You can get more information about OSVVM at or at

Get training in our VHDL Testbenches and Verification - OS-VVM Boot Camp. See
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