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Re: Compiler Question

 
 
goouse99@gmail.com
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      04-23-2013
Am Dienstag, 23. April 2013 05:21:20 UTC+2 schrieb VerilogNewb:
> Hello,
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>
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> I'm new to this group and new to Verilog and am having a compiler error for what i hope is a simple syntax mistake. I'm a first year college student with a little background in Java, that might show in how I wrote my verilog code...
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> I'd rather not put my entire code onto this page since sharing projects between students would constitute cheating and if someone sniped it I'd never know until it was too late...
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> So I'll post a general area of where I'm getting an error, and if you can see what I'm doing wrong, that'd be nice but if you would like to see the rest just let me know.
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> ERRORS IM RECEIVING:
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> Error (10170): Verilog HDL syntax error at controller.v(25) near text "always"; expecting "end"
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> Error (10170): Verilog HDL syntax error at controller.v(43) near text "always"; expecting "end"
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> Error (10170): Verilog HDL syntax error at controller.v(165) near text "always"; expecting "end"
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> Error (10170): Verilog HDL syntax error at controller.v(18 near text "always"; expecting "end"
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> Error (10112): Ignored design unit "controller" at controller.v(1) due to previous errors
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> Info: Found 0 design units, including 0 entities, in source file controller.v
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> Error: Quartus II Analysis & Synthesis was unsuccessful. 5 errors, 0 warnings
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> Error: Peak virtual memory: 199 megabytes
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> Error: Processing ended: Mon Apr 22 22:02:24 2013
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> Error: Elapsed time: 00:00:00
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> Error: Total CPU time (on all processors): 00:00:00
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> Error: Quartus II Full Compilation was unsuccessful. 7 errors, 0 warnings
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> -----------------------------------------------------------------
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> A sample of my code with most of the case statement info removed:
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> always @ (posedge clk) begin
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> always @ (posedge enter) begin
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> case (inputState)
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> endcase // end case 1
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> end // end inner always 1
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> always @ (inputState) begin
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> case (inputState)
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> endcase // end case 2
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> end // end inner always 2
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> end // end outer always
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> -----------------------------------------------------------------
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> the first error happens at the second always @:
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> "always @ (posedge clk) begin"
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> but i know its connected to the end at my line 41 which is the end at:
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> "end // end inner always 1"
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> the second error happens at the third always @:
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> "always @ (inputState) begin"
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> but i know its connected to the end at my line 58 which is the end at:
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> "end // end inner always 2"
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> The other two syntax errors happen later in the code but in similiar circumstance (2 always @ statements within another always @ statement)
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> Is there an issue of trying to have an always @ statement within another always @ statement?
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> Any help you could give would be appreciated.


Hi,
this is comp.lang.VHDL
so you are quite wrong here.
You should choose to post on comp.lang.verilog instead.

Have a nice synthesis
Eilert
 
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