Velocity Reviews > VHDL > Mathematical formula implementation

# Mathematical formula implementation

rickman
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Posts: n/a

 03-16-2013
On 3/15/2013 10:07 PM, chrisabele wrote:
> On 3/15/2013 6:29 PM, rickman wrote:
>> On 3/15/2013 6:25 PM, Rob Gaddi wrote:
>>> On Thu, 14 Mar 2013 22:13:53 -0400
>>> rickman<(E-Mail Removed)> wrote:
>>>
>>>> On 3/14/2013 6:23 PM, vhdl_newbie wrote:
>>>>> Hello,
>>>>> I am a beginner with learn VHDL and I need to implement a
>>>>> mathematical formula for a job interview.
>>>>> I have one day to solve this problem so if there is any good
>>>>> samaritan that could help me with this problem, I would really
>>>>> appreciate it.
>>>>>
>>>>> solve this formula for Y
>>>>>
>>>>> Y=(P^2+K*P)/16
>>>>>
>>>>> with
>>>>>
>>>>> P = [0:63]
>>>>> K = [0:4]
>>>>> Y = [0:512]
>>>>>
>>>>> Have a nice day !
>>>>
>>>> If this were a real requirement, I would say there was something wrong
>>>> with it. It could be coded, but it would be hard to actually build. If
>>>> P is a 64 bit integer, it has a range of 0 to 2^64-1. As an exponent of
>>>> K, the result would have 2^64+4 bits. I don't know how to represent
>>>> that in a way that VHDL would understand. Heck, my calculator threw up
>>>> when I tried to calculate it.
>>>>
>>>> Are you sure this is the right question? I can't see any value in
>>>> asking a job candidate such a question.
>>>>
>>>> WAIT! The notation is wonkey! You mean the variables have his range,
>>>> not that many bits, right? That's different. But it still doesn't fit.
>>>> You can't shove the result into the range for Y.
>>>>
>>>> Maybe that's what they want you to tell them?
>>>>
>>>
>>> I think you're misreading. That's (P^P+K*P)/16, or P(P+K)/16

>>
>> Yes, you are right. I misread the problem. Wouldn't be the first time
>> and won't be the last...
>>
>> But the problem remains. If those are ranges, the general result won't
>> fit in the variable Y.
>>

>
> I think Rob's rewriting is really helpful (aside from his forgetting to
> change the ^ to a *). And if we assume that the values in [] are value
> ranges rather than bit index ranges then the maximum Y value would be
> 63*(63+4)/16 = 264 which certainly is within the range [0:512]. Of
> course I've assumed that Y must be an integer and truncated (actually
> rounded) the result, plus the intermediate result is certainly much
> larger than 512. But given those assumptions the problem is not
> unreasonable. So perhaps the code that Paul posted is the best answer.
>
> Perhaps the point of the interview question was to see if the candidate
> would raise exactly the issues that have been discussed this thread...

Yes, I forgot to divide by 16, I was only looking at the multiplications.

I still think it is a bit of an odd question for a job interview, but I
suppose it must relate to something the company does, or maybe the
interviewer just picked this as an example question without any real
reason.

had solved a very tough problem before. Immediately a problem came to
mind that I had done a couple of years before and had stumped me for a
few days before coming up with a solution. Unfortunately I couldn't
recall the solution! So much for thinking on your feet.

Needless to say, I didn't get the job...

--

Rick

rickman
Guest
Posts: n/a

 03-16-2013
On 3/14/2013 6:23 PM, vhdl_newbie wrote:
> Hello,
> I am a beginner with learn VHDL and I need to implement a mathematical formula for a job interview.
> I have one day to solve this problem so if there is any good samaritan that could help me with this problem, I would really appreciate it.
>
> solve this formula for Y
>
> Y=(P^2+K*P)/16
>
> with
>
> P = [0:63]
> K = [0:4]
> Y = [0:512]
>
> Have a nice day !

into the interview trying to give the impression that you "know" VHDL.
You are clearly a beginner and that will show in the interview. What
you should consider is trying to learn a bit about VHDL and let them
know that you are coming up the learning curve.

One of the big difficulties beginners have with VHDL is the strong
typing. Learn how to convert between the different types, when you need
to do what type of conversion and why. If you can explain all this in
an interview I think it will impress anyone. If I were interviewing
someone as a VHDL designer and they could articulate a good approach to
type conversions I know I would be favorably impressed. I expect a lot
of people here can't do that.

--

Rick

vhdl_newbie
Guest
Posts: n/a

 03-18-2013

Hello,
Thanks a lot for all of you answer, it was pretty helpful for me. So, for those asking, I already did the interview. It was only afterwards that they asked me to solve a VHDL problem. Also, I think the [] was meant to be the range for the integers. So I came up with this, from your what I had the time to learn in one day. Don't bother correcting it, I had to send it quickly so it is too late to change it now. I send it in case it could interest someone.
Thanks again for the help !

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;

entity formule is
port (
K : in Unsigned(2 downto 0); -- 3 bits for [0:4]
P : in Unsigned(5 downto 0); -- 6 bits for [0:64]
Y : out Unsigned(9 downto 0); -- 10 bits for [0:512]
);
end formule;

architecture arch of formule is

-- refactorizing : Y=P*(P+K)/16

Signal sum : Unsigned(6 downto 0); -- 7 bits for (P+K)
Signal numerator : Unsigned(12 downto 0); -- 13 bits for P*(P+K)

begin

sum <= P + K;
numerator <= P * sum;
Y <= numerator srl 4; -- I shift the numbers 4 bits to the right to divide by 16 (someone told me "/" doesnt work all the time)

end arch;

rickman
Guest
Posts: n/a

 03-19-2013
On 3/17/2013 10:47 PM, vhdl_newbie wrote:
>
> Hello,
> Thanks a lot for all of you answer, it was pretty helpful for me. So, for those asking, I already did the interview. It was only afterwards that they asked me to solve a VHDL problem. Also, I think the [] was meant to be the range for the integers. So I came up with this, from your what I had the time to learn in one day. Don't bother correcting it, I had to send it quickly so it is too late to change it now. I send it in case it could interest someone.
> Thanks again for the help !
>
>
> library IEEE;
> use IEEE.Std_Logic_1164.all;
> use IEEE.Numeric_Std.all;
>
> entity formule is
> port (
> K : in Unsigned(2 downto 0); -- 3 bits for [0:4]
> P : in Unsigned(5 downto 0); -- 6 bits for [0:64]
> Y : out Unsigned(9 downto 0); -- 10 bits for [0:512]
> );
> end formule;
>
> architecture arch of formule is
>
> -- refactorizing : Y=P*(P+K)/16
>
> Signal sum : Unsigned(6 downto 0); -- 7 bits for (P+K)
> Signal numerator : Unsigned(12 downto 0); -- 13 bits for P*(P+K)
>
> begin
>
> sum<= P + K;
> numerator<= P * sum;
> Y<= numerator srl 4; -- I shift the numbers 4 bits to the right to divide by 16 (someone told me "/" doesnt work all the time)
>
> end arch;

I can't resist. This is pretty good, but you didn't allow enough range
for P. It is 0 to 64, not 0 to 63. So you need 7 bits. sum still only
needs 7 bits because the sum won't exceed this range given the input
constraints.

Otherwise this is good for a beginner.

--

Rick

Andy
Guest
Posts: n/a

 03-19-2013
Me neither (can't resist).

Given the non-power-of two ranges involved, I would keep this in the integer domain:

K: in natural range 0 to 4;
P: in natural range 0 to 64;
Y: out natural range 0 to 64 * (64 + 4) / 16; -- 9 bits is enough
....

Y <= P * (P + K) / 16;

Synthesis tools recognize a multiply/divide by a constant power of two as a shift operation anyway.

Keep in mind, if you are trying to use built-in MAC blocks in an FPGA, this needs to be pipelined across multiple clock cycles. Otherwise a combinatorial implementation is going to be very slow and large.

Andy

vhdl_newbie
Guest
Posts: n/a

 03-22-2013
Hello,
Thanks for the advices, Andy and Rick, i'll try the keep them in mind.
Again, thanks a lot for your help, you are a great community !