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Set std_logic_vector values in a range

 
 
anasimtiaz@gmail.com
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      03-01-2013
Hi,

I have two vectors a1 and a2, e.g.

a1: 0 0 1 0 0 0 0 0 0
a2: 0 0 0 0 0 0 0 1 0

a3 is a vector that OR's the two:
a3: 0 0 1 0 0 0 0 1 0

I want to create a mask from this a4 such that
a4: 0 0 1 1 1 1 1 1 0
and use this as the enable signal downstream. I want to update the registers that are between the 1's I get in a1 and a2. Whats the best way to get a4 from a1 and a2?

Many thanks
 
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Rob Gaddi
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      03-01-2013
On Fri, 1 Mar 2013 08:22:41 -0800 (PST)
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:

> Hi,
>
> I have two vectors a1 and a2, e.g.
>
> a1: 0 0 1 0 0 0 0 0 0
> a2: 0 0 0 0 0 0 0 1 0
>
> a3 is a vector that OR's the two:
> a3: 0 0 1 0 0 0 0 1 0
>
> I want to create a mask from this a4 such that
> a4: 0 0 1 1 1 1 1 1 0
> and use this as the enable signal downstream. I want to update the registers that are between the 1's I get in a1 and a2. Whats the best way to get a4 from a1 and a2?
>
> Many thanks


If you define a1 and a2 as unsigned, and you know a1 will always be
larger than a2 (as it currently is), then I believe that your a4 is
simply (a1-a2) or a1.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.
 
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GaborSzakacs
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      03-01-2013
Rob Gaddi wrote:
> On Fri, 1 Mar 2013 08:22:41 -0800 (PST)
> (E-Mail Removed) wrote:
>
>> Hi,
>>
>> I have two vectors a1 and a2, e.g.
>>
>> a1: 0 0 1 0 0 0 0 0 0
>> a2: 0 0 0 0 0 0 0 1 0
>>
>> a3 is a vector that OR's the two:
>> a3: 0 0 1 0 0 0 0 1 0
>>
>> I want to create a mask from this a4 such that
>> a4: 0 0 1 1 1 1 1 1 0
>> and use this as the enable signal downstream. I want to update the registers that are between the 1's I get in a1 and a2. Whats the best way to get a4 from a1 and a2?
>>
>> Many thanks

>
> If you define a1 and a2 as unsigned, and you know a1 will always be
> larger than a2 (as it currently is), then I believe that your a4 is
> simply (a1-a2) or a1.
>

Of course that assumes that a1 and a2 will never have more than one
bit set, which wasn't explicitly stated in the OP. Is this the case?

-- Gabor
 
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GaborSzakacs
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      03-01-2013
GaborSzakacs wrote:
> Rob Gaddi wrote:
>> On Fri, 1 Mar 2013 08:22:41 -0800 (PST)
>> (E-Mail Removed) wrote:
>>
>>> Hi,
>>>
>>> I have two vectors a1 and a2, e.g.
>>>
>>> a1: 0 0 1 0 0 0 0 0 0 a2: 0 0 0 0 0 0 0 1 0
>>>
>>> a3 is a vector that OR's the two:
>>> a3: 0 0 1 0 0 0 0 1 0
>>>
>>> I want to create a mask from this a4 such that
>>> a4: 0 0 1 1 1 1 1 1 0
>>> and use this as the enable signal downstream. I want to update the
>>> registers that are between the 1's I get in a1 and a2. Whats the best
>>> way to get a4 from a1 and a2?
>>>
>>> Many thanks

>>
>> If you define a1 and a2 as unsigned, and you know a1 will always be
>> larger than a2 (as it currently is), then I believe that your a4 is
>> simply (a1-a2) or a1.

> Of course that assumes that a1 and a2 will never have more than one
> bit set, which wasn't explicitly stated in the OP. Is this the case?
>
> -- Gabor

Forgot to add, it also assumes that the '1' bit in a1 is
always to the left of the '1' bit in a2. If not, you'd
need to do a comparison before subtracting or an absolute
value after subtracting.

-- Gabor
 
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anasimtiaz@gmail.com
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      03-04-2013
Thank you! I think I'll have to OR the result of subtraction with a1 to get a4 in the end but that solves the issue! And yes, only a bit of a1 and a2 would be '1' at any time.
 
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Andy
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      03-04-2013
Have you tried a simple for-loop with a couple of variable flags?

a4 <= (others => '0'); -- default assignments
start_flag := false;
stop_flag := false;
for i in a1'range loop
if a1(i) = '1' then
start_flag := true;
end if;
if start_flag and not stop_flag then
a4(i) <= '1';
end if;
if a2(i) = '1' then -- set stop_flag _after_ this bit
stop_flag := true;
end if;
end loop;

It would be interesting to compare the results.

If you are wondering how this might work in HW, just remember that synthesis unrolls all for-loops.

Andy
 
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