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Assign a value to a position in a std_logic_vector

 
 
Thomas Stanka
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      02-27-2013
On 26 Feb., 15:54, (E-Mail Removed) wrote:
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;


Not your question but usage of these libraries is bad style. You will
see them a lot in old books and unfortunately too often in even not so
old books).

Use ieee.numeric_std.all instead. The _arith and _unsigned itself are
vendor dependent, while numeric_std is real ieee standard and
therefore vendor independent.

> * * * * process (RdData2)
> * * * * * begin
> * * * * * * * * OP3 <= RdData2;
> * * * * end process;
> * * * * with Sa select
> * * * * * * * * S_nat <= 0 when "00000",1 when "00001",2 when "00010",3 when "00011",4 when "00100",5 when "00101",
> * * * * * * * * * * * * * * * * * * * * 6 when "00110",7 when "00111",8 when "01000",9 when "01001",10 when"01010",11 when "01011",
> * * * * * * * * * * * * * * * * * * * * 12 when "01100",13 when "01101",14 when "01110",15 when "01111",16 when "10000",17 when "10001",
> * * * * * * * * * * * * * * * * * * * * 18 when "10010",19 when "10011",20 when "10100",21 when "10101",22 when "10110",23 when "10111",
> * * * * * * * * * * * * * * * * * * * * 24 when "11000",25 when "11001",26 when "11010",27 when "11011",28 when "11100",29 when "11101",
> * * * * * * * * * * * * * * * * * * * * 30 when "11110",31 when others;
>
> * * * * process (S_nat)
> * * * * * * * * begin
> * * * * OP3(S_nat) <= '1';
> * * * * end process;


Better:

process (Rddata2, Sa)
begin
OP3 <= RdData2; -- initailise all bits of
OP3 with RdData2
OP3(to_integer(unsigned(Sa))) <= '1'; -- modify bit selected
with Sa
end process;

This code eliminates the fact that two process drive the same signal,
is by far more readable and less errorprone than the code above.
It is important that if you use some branches, each branch defines all
bits of signal even if you would use OP3 <= OP3; OP3(Sa) <= '1'.

bye Thomas
 
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