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Why ever use std_logic_vector intead of signed/unsigned?

 
 
kevin.neilson@xilinx.com
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      02-21-2013
I'm getting back into VHDL after a long absence, and I can't find an answerto this question. When would I ever use std_logic_vector? If I were starting a new design, with current tools, I could used 'signed' and 'unsigned', even for the ports, and use numeric_std, and everything is cleaner. Is there any situation in which std_logic_vector might be required? There mustbe, or it wouldn't still exist.
 
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Rob Gaddi
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      02-21-2013
On Wed, 20 Feb 2013 16:42:53 -0800 (PST)
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:

> I'm getting back into VHDL after a long absence, and I can't find an answer to this question. When would I ever use std_logic_vector? If I were starting a new design, with current tools, I could used 'signed' and 'unsigned', even for the ports, and use numeric_std, and everything is cleaner. Is there any situation in which std_logic_vector might be required? There must be, or it wouldn't still exist.


There are ZILLIONS of tools you'll use along the way that won't let you
use anything but std_logic/std_logic_vector. Not the least of which
being Xilinx CoreGen.

More to the point, there's a conceptual difference there. Signed and
unsigned represent numbers, things that have the concepts of addition
and comparison, etc, defined. std_logic_vector represents arbitrary
collections of bits, such as collections of flags, bytes in and out of a
UART, etc.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.
 
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Thomas Stanka
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      02-21-2013
On 21 Feb., 01:42, (E-Mail Removed) wrote:
> I'm getting back into VHDL after a long absence, and I can't find an answer to this question. *When would I ever use std_logic_vector? *If I were starting a new design, with current tools, I could used 'signed' and 'unsigned', even for the ports, and use numeric_std, and everything is cleaner.*Is there any situation in which std_logic_vector might be required? *There must be, or it wouldn't still exist.


Required might be the wrong word. But if your not talking about
numbers, it is for me more intiuitive to use stl-vector.
Assume you have a bus of control-signals going to different modules or
external components e.g Chip_Sel(3 downto 0), using that as unsigned
works, but makes it less intuitive. If you split this into two signals
CS_left and CS_right with both beeing 2 bit width your not lost, but
do things that are not intuitive for me when dealing with unsigned/
signed.

A more important point is that I'm still member of the std_ulogic
faction, as this helps finding some problems in design during compile,
instead of waiting till netlist to detect that you have two driver
where you intended to have only one. As ulogic-fan I see ofc way more
reasons to use vector instead of unsingned/signed.

best regards Thomas
 
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valtih1978
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      02-21-2013
> More to the point, there's a conceptual difference there. Signed and
> unsigned represent numbers, things that have the concepts of addition
> and comparison, etc, defined. std_logic_vector represents arbitrary
> collections of bits, such as collections of flags, bytes in and out of a
> UART, etc.


You cannot go to shopping with the same car you travel to work. There is
a conceptual difference.

You cannot travel to work in a car, equipped with audio system. There
are a huge number of concepts related with music, radio and audio.
Simple car is intended for transporting people. You cannot transport
people in a car equipped with audio system. It can be done only when you
need people to listen music in the transport.


 
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valtih1978
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      02-21-2013
When you travel in a car with audio off, your intent is not clear. Do
you want to travel or just listen the music?
 
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Rob Gaddi
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      02-21-2013
On Thu, 21 Feb 2013 20:09:17 +0200
valtih1978 <(E-Mail Removed)> wrote:

> > More to the point, there's a conceptual difference there. Signed and
> > unsigned represent numbers, things that have the concepts of addition
> > and comparison, etc, defined. std_logic_vector represents arbitrary
> > collections of bits, such as collections of flags, bytes in and out of a
> > UART, etc.

>
> You cannot go to shopping with the same car you travel to work. There is
> a conceptual difference.
>
> You cannot travel to work in a car, equipped with audio system. There
> are a huge number of concepts related with music, radio and audio.
> Simple car is intended for transporting people. You cannot transport
> people in a car equipped with audio system. It can be done only when you
> need people to listen music in the transport.
>


If you don't like strong typing, write Verilog. The lack of
mathematical operations defined on std_logic_vector means that it is a
compile-time error to try to perform math on anything not explicitly
defined as being signed or unsigned.

It's the same as using range restricted integer subtypes, it allows
your code to be more explicit about what is and is not going to happen,
and what things do or do not mean. That's not for the tools' benefit,
it's for the programmer's.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.
 
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kevin.neilson@xilinx.com
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      02-21-2013
This metaphor makes no sense. Of course I travel to work in the same car that I shop in.
 
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Andy
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      02-21-2013
On Feb 21, 12:19*pm, Rob Gaddi <(E-Mail Removed)>
wrote:
> If you don't like strong typing, write Verilog.


Whoa! No need to use a broken, "hold my beer and watch this" excuse
for a language like verilog!

If your tools support a smidgen of VHDL-2008, you can use
ieee.numeric_std_unsigned, which conveys all of the arithmetic
abilities of numeric_std_unsigned onto std_logic_vector. It's like the
old std_logic_unsigned package, only standard and better.

Also under VHDL-2008, std_logic_vector is a (resolved) subtype of
std_ulogic_vector, so they can be assigned to, or associated with,
each other without conversion. This makes it much easier to use SUL/
SUV to catch multiple driver issues at compile time, just without the
previous conversion hassle.

If your tool vendor doesn't support at least this much of VHDL-2008
yet, call them and tell them their competition does.

There are LOTS of other very nice enhancements to VHDL in 2008, some
of which are not yet well supported by the tools. Call and complain,
and threaten to switch tools!

Andy
 
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rickman
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      02-22-2013
On 2/21/2013 1:19 PM, Rob Gaddi wrote:
> On Thu, 21 Feb 2013 20:09:17 +0200
> valtih1978<(E-Mail Removed)> wrote:
>
>>> More to the point, there's a conceptual difference there. Signed and
>>> unsigned represent numbers, things that have the concepts of addition
>>> and comparison, etc, defined. std_logic_vector represents arbitrary
>>> collections of bits, such as collections of flags, bytes in and out of a
>>> UART, etc.

>>
>> You cannot go to shopping with the same car you travel to work. There is
>> a conceptual difference.
>>
>> You cannot travel to work in a car, equipped with audio system. There
>> are a huge number of concepts related with music, radio and audio.
>> Simple car is intended for transporting people. You cannot transport
>> people in a car equipped with audio system. It can be done only when you
>> need people to listen music in the transport.
>>

>
> If you don't like strong typing, write Verilog. The lack of
> mathematical operations defined on std_logic_vector means that it is a
> compile-time error to try to perform math on anything not explicitly
> defined as being signed or unsigned.
>
> It's the same as using range restricted integer subtypes, it allows
> your code to be more explicit about what is and is not going to happen,
> and what things do or do not mean. That's not for the tools' benefit,
> it's for the programmer's.


I think you are over-thinking the value and purpose of strong typing.
There is nothing about signed/unsigned types that should preclude the
their use in interfaces to memories, multipliers, or any other device
whether it is made by coregen or other tools. It is not an issue of the
user wanting to do math on non-math items. The user is asking why can't
he use the *appropriate* type of signal in an interface.

I think the restriction of tools to using slv is just inertia. It
works, so don't break it by improving it. The laws of unintended
consequences are a harsh teacher.

--

Rick
 
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kevin.neilson@xilinx.com
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      02-22-2013
This is the idea I'm getting. I haven't gotten a good answer about why I should ever use slv, and I'm getting the idea it's only still around because of inertia. The responses seem to be:
1. SLV is better *because* of its limitations. You *could* use signed/unsigned, but why, when you could use something that does even less?
2. But wait: with the new 2008 libraries, SLV is about as good as signed/unsigned. (So why not just use signed/unsigned?)
3. Other cores like CoreGen cores will use SLV, so you have to also in order to interface them. (This is valid, although I try to avoid CoreGen when possible, and I can always convert, possibly even in the instantiation with 2008.)
 
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