Velocity Reviews > VHDL > noob question on loops

# noob question on loops

Karol Hennessy
Guest
Posts: n/a

 01-21-2013
I'm currently trying to work through some examples in one of Pong Chu's books. *There's one thing I'm not quite clear on. *In many of his exampleshe uses lots of if .. else statements, but hardly ever for loops. *In some of the questions, you're asked to extend some example he has given, e.g.going from say 4bit input to 12bit or something like that.

For this kind of example, it seems natural to me to use some sort of loop for each of the 12bits. *Is this poor practice?

One example he gives is a priority encoder, where you output the highest bit that is set to 1. *If we have 4 bit input and 3 bit output, we would have

in * * *out*
"1XXX"*"100" (4)
"01XX" "011" (3)
"001X" "010" (2)
"0001" "001" (1)
"0000" "000" (0)

If we had some 32bit input std_logic_vector, would we really have to explicitly code each case or is there some sort of looping we can use? *What isthe preferred method to deal with long std_logic_vectors?

GaborSzakacs
Guest
Posts: n/a

 01-21-2013
Karol Hennessy wrote:
> I'm currently trying to work through some examples in one of Pong Chu's books. There's one thing I'm not quite clear on. In many of his examples he uses lots of if .. else statements, but hardly ever for loops. In some of the questions, you're asked to extend some example he has given, e.g. going from say 4bit input to 12bit or something like that.
>
> For this kind of example, it seems natural to me to use some sort of loop for each of the 12bits. Is this poor practice?
>
> One example he gives is a priority encoder, where you output the highest bit that is set to 1. If we have 4 bit input and 3 bit output, we would have
>
> in out
> "1XXX" "100" (4)
> "01XX" "011" (3)
> "001X" "010" (2)
> "0001" "001" (1)
> "0000" "000" (0)
>
> If we had some 32bit input std_logic_vector, would we really have to explicitly code each case or is there some sort of looping we can use? What is the preferred method to deal with long std_logic_vectors?

Loops are a perfectly valid way to implement a priority encoder. Often
textbooks are very behind the curve in synthesis technology, and it
wasn't that long ago that many synthesis tools had poor if any
support for loops. Also it is generally not a good idea for beginners
to start thinking in terms of loops until they have an understanding
of the potentially large hardware that a loop creates when it gets
unrolled.

I'm most familiar with Xilinx tools, where there are some strict
restriction on loops, especially that the number of iterations
must be a constant at synthesis time. So in the case of a 32-bit
priority encode, your loop for simulation would probably work
best if it is coded to exit as soon as the first '1' bit is
found. But for synthesis, at least for XST, you'd code it with
a variable to remember that the first one has already been found and
an if statement to prevent further assignments on the remining
loop iterations.

-- Gabor

rickman
Guest
Posts: n/a

 01-21-2013
On 1/21/2013 1:51 PM, GaborSzakacs wrote:
> Karol Hennessy wrote:
>> I'm currently trying to work through some examples in one of Pong
>> Chu's books. There's one thing I'm not quite clear on. In many of his
>> examples he uses lots of if .. else statements, but hardly ever for
>> loops. In some of the questions, you're asked to extend some example
>> he has given, e.g. going from say 4bit input to 12bit or something
>> like that.
>>
>> For this kind of example, it seems natural to me to use some sort of
>> loop for each of the 12bits. Is this poor practice?
>>
>> One example he gives is a priority encoder, where you output the
>> highest bit that is set to 1. If we have 4 bit input and 3 bit output,
>> we would have
>>
>> in out "1XXX" "100" (4)
>> "01XX" "011" (3)
>> "001X" "010" (2)
>> "0001" "001" (1)
>> "0000" "000" (0)
>>
>> If we had some 32bit input std_logic_vector, would we really have to
>> explicitly code each case or is there some sort of looping we can use?
>> What is the preferred method to deal with long std_logic_vectors?

>
> Loops are a perfectly valid way to implement a priority encoder. Often
> textbooks are very behind the curve in synthesis technology, and it
> wasn't that long ago that many synthesis tools had poor if any
> support for loops. Also it is generally not a good idea for beginners
> to start thinking in terms of loops until they have an understanding
> of the potentially large hardware that a loop creates when it gets
> unrolled.
>
> I'm most familiar with Xilinx tools, where there are some strict
> restriction on loops, especially that the number of iterations
> must be a constant at synthesis time. So in the case of a 32-bit
> priority encode, your loop for simulation would probably work
> best if it is coded to exit as soon as the first '1' bit is
> found. But for synthesis, at least for XST, you'd code it with
> a variable to remember that the first one has already been found and
> an if statement to prevent further assignments on the remining
> loop iterations.

I've been coding in VHDL for some 15+ years and I can't remember using
loops for synthesized code once. But I think a priority encoder would
be a perfect use of a loop. I would loop from the lowest priority bit
to the highest priority bit and overwrite the variable with the
corresponding bit number each time it is a one. At the end of the loop
the variable is set to the right value and can be assigned to a signal.
BTW, do you plan to have a separate signal to indicate the presence of
a 1 bit in the word or will you use a zero code for no bits set and use
a 1 based count for the msb bit position requiring a 6 bit priority word?

I would code this unit separately and test it in synthesis to see what
is produced. It should produce the priority chain of gates or more
likely optimize it to something not so easily recognizable. But it
would be interesting to see if it is reasonably efficient. At 32 bits a
priority encoder can be pretty messy.

Rick

Andy
Guest
Posts: n/a

 01-22-2013
On Monday, January 21, 2013 1:57:43 PM UTC-6, rickman wrote:
> On 1/21/2013 1:51 PM, GaborSzakacs wrote: > Karol Hennessy wrote: >> I'm currently trying to work through some examples in one of Pong >> Chu's books. There's one thing I'm not quite clear on. In many of his >> examples he uses lots of if .. else statements, but hardly ever for >> loops. In some of the questions, you're asked to extend some example >> he has given, e.g. going from say 4bit input to 12bit or something >> like that. >> >> For this kind of example, it seems natural to me to use some sort of >> loop for each of the 12bits. Is this poor practice? >> >> One example he gives is a priority encoder, where you output the >> highest bit that is set to 1. If we have 4 bit input and 3 bit output, >> we would have >> >> in out "1XXX" "100" (4) >> "01XX" "011" (3) >> "001X" "010" (2) >> "0001" "001" (1) >> "0000" "000" (0) >> >> If we had some 32bit input std_logic_vector, would we really have to >> explicitly code each case or is there some sort of loopingwe can use? >> What is the preferred method to deal with long std_logic_vectors? > > Loops are a perfectly valid way to implement a priority encoder.Often > textbooks are very behind the curve in synthesis technology, and it > wasn't that long ago that many synthesis tools had poor if any > support for loops. Also it is generally not a good idea for beginners > to start thinking in terms of loops until they have an understanding > of the potentially large hardware that a loop creates when it gets > unrolled. > > I'm most familiar with Xilinx tools, where there are some strict > restriction on loops, especially that the number of iterations > must be a constant at synthesis time. So in the case of a 32-bit > priority encode, your loop for simulation would probably work > best if it is coded to exit as soon as thefirst '1' bit is > found. But for synthesis, at least for XST, you'd code it with > a variable to remember that the first one has already been found and > an if statement to prevent further assignments on the remining > loopiterations. I've been coding in VHDL for some 15+ years and I can't remember using loops for synthesized code once. But I think a priority encoder would be a perfect use of a loop. I would loop from the lowest priority bit to the highest priority bit and overwrite the variable with the corresponding bit number each time it is a one. At the end of the loop the variable is set to the right value and can be assigned to a signal. BTW, do you plan tohave a separate signal to indicate the presence of a 1 bit in the word or will you use a zero code for no bits set and use a 1 based count for the msb bit position requiring a 6 bit priority word? I would code this unit separately and test it in synthesis to see what is produced. It should produce the priority chain of gates or more likely optimize it to something not so easily recognizable. But it would be interesting to see if it is reasonablyefficient. At 32 bits a priority encoder can be pretty messy. Rick

If you are not comfortable or familiar with using loops in synthesis, I stronly agree that caution is necessary.

IMHO, most university courseware for HDL based design does a miserable job of covering basic SW techniques that are fully applicable to HW design. So unless one snoops around on their own, purchases the right book, or gets advanced training, they are unlikely to understand or use these techniques. That is not to say that you can't design reliable HW without these techniques, but it is much harder to develop maintainable, reliable designs without them.

I've been designing programmable HW with VHDL for going on 21 years now, and for most of those I have used loops in synthesis with excellent results. The key is understanding how the loop's behavior tranlates into hardware, and whatever restrictions synthesis tools have on their use.

In virtually all synthesis tools, loops are supported, as long as they don't contain a wait statement. Thus they iterate in zero time/deltas. Among other things, this means that a signal assigned in one iteration will not be updated for subsequent iterations. If you need something like that (e.g. parity), use a variable to hold the value, so the updated value is available in later iterations.

Simply stated, synthesis unrolls loops, and therefore requires a static (known at synthesis time) limit for the loop so that the correct number of iterations to unroll is known. You can use a conditional exit statement with adynamic value to terminate the loop (this unrolls to a long if-elsif-elsif.... statement).

The resulting hardware is identical whether you used a loop or wrote out N copies of the loop's statements manually.

Just like a SW, loops are critical structures for handling lots of situations in elegant, understandable and maintainable code. In VHDL you can invokethe 'range attribute of an array in the for loop statement to automatically iterate over each item in the array. You can also use 'reverse_range to iterate backwards. Using these tricks not only makes the code more reliable,it allows you to tell (in a verifiable, executable statement, not a comment) the user WHAT your are iterating on (kinda like a foreach).

Andy

valtih1978
Guest
Posts: n/a

 01-22-2013
> a wait statement

Wait. My teacher taught me that "a" means "one" in English. And, this is
what all synthesizers want in VHDL -- one and only one wait.

rickman
Guest
Posts: n/a

 01-23-2013
On 1/22/2013 11:56 AM, Andy wrote:
> On Monday, January 21, 2013 1:57:43 PM UTC-6, rickman wrote:
>> On 1/21/2013 1:51 PM, GaborSzakacs wrote:> Karol Hennessy wrote:>> I'm currently trying to work through some examples in one of Pong>> Chu's books. There's one thing I'm not quite clear on. In many of his>> examples he uses lots of if .. else statements, but hardly ever for>> loops. In some of the questions, you're asked to extend some example>> he has given, e.g. going from say 4bit input to 12bit or something>> like that.>> >> For this kind of example, it seems natural to me to use some sort of>> loop for each of the 12bits. Is this poor practice?>> >> One example he gives is a priority encoder, where you output the>> highest bit that is set to 1. If we have 4 bit input and 3 bit output,>> we would have>> >> in out "1XXX" "100" (4)>> "01XX" "011" (3)>> "001X" "010" (2)>> "0001" "001" (1)>> "0000" "000" (0)>> >> If we had some 32bit input std_logic_vector, would we really have to>> explicitly code each case or is there some sort of looping we can use?>> W

hat is the preferred method to deal with long std_logic_vectors?> > Loops are a perfectly valid way to implement a priority encoder. Often> textbooks are very behind the curve in synthesis technology, and it> wasn't that long ago that many synthesis tools had poor if any> support for loops. Also it is generally not a good idea for beginners> to start thinking in terms of loops until they have an understanding> of the potentially large hardware that a loop creates when it gets> unrolled.> > I'm most familiar with Xilinx tools, where there are some strict> restriction on loops, especially that the number of iterations> must be a constant at synthesis time. So in the case of a 32-bit> priority encode, your loop for simulation would probably work> best if it is coded to exit as soon as the first '1' bit is> found. But for synthesis, at least for XST, you'd code it with> a variable to remember that the first one has already been found and> an if statement to prevent furth
er assignments on the remining> loop iterations. I've been coding in VHDL for some 15+ years and I can't remember using loops for synthesized code once. But I think a priority encoder would be a perfect use of a loop. I would loop from the lowest priority bit to the highest priority bit and overwrite the variable with the corresponding bit number each time it is a one. At the end of the loop the variable is set to the right value and can be assigned to a signal. BTW, do you plan to have a separate signal to indicate the presence of a 1 bit in the word or will you use a zero code for no bits set and use a 1 based count for the msb bit position requiring a 6 bit priority word? I would code this unit separately and test it in synthesis to see what is produced. It should produce the priority chain of gates or more likely optimize it to something not so easily recognizable. But it would be interesting to see if it is reasonably efficient. At 32 bits a priority encoder can be pretty messy
.. Rick
>
> If you are not comfortable or familiar with using loops in synthesis, I stronly agree that caution is necessary.
>
> IMHO, most university courseware for HDL based design does a miserable job of covering basic SW techniques that are fully applicable to HW design. So unless one snoops around on their own, purchases the right book, or gets advanced training, they are unlikely to understand or use these techniques. That is not to say that you can't design reliable HW without these techniques, but it is much harder to develop maintainable, reliable designs without them.

....snip...
>
> Andy

I never said I was "not comfortable" or familiar with using loops in
synthesis. I said I hadn't used one that I can recall, meaning I've
found little need. I don't recall ever coding a priority encoder which
is one function that can be easily with a loop. Otherwise I can't think
of any functions that are easier or better described with a loop.

Can you give some common examples of loops in synthesis?

Rick

HT-Lab
Guest
Posts: n/a

 01-23-2013
On 22/01/2013 23:16, Alan Fitch wrote:
> On 22/01/13 20:04, valtih1978 wrote:
>> > a wait statement

>>
>> Wait. My teacher taught me that "a" means "one" in English. And, this is
>> what all synthesizers want in VHDL -- one and only one wait.
>>

>
> I don't think that's completely true.
>
> I seem to remember that Leonardo Spectrum could understand an implicit
> state machine coding style which had multiple wait statements in a
> single process.
>
> But I haven't tried that out recently with modern tools.

Mentor's Precision can and I assume Synplify as well,

process
begin
wait until clk'event AND clk='1';
output_signal <= 0;
while (input_signal < 6) loop
wait until clk'event AND clk='1';
output_signal <= output_signal+1;
end loop;
end process;

Regards,
Hans
www.ht-lab.com

I always tell
> people on training courses to only use one wait in a synthesisable
> process
>
> regards
> Alan
>

GaborSzakacs
Guest
Posts: n/a

 01-23-2013
Alan Fitch wrote:
> On 22/01/13 20:04, valtih1978 wrote:
>> > a wait statement

>>
>> Wait. My teacher taught me that "a" means "one" in English. And, this is
>> what all synthesizers want in VHDL -- one and only one wait.
>>

>
> I don't think that's completely true.
>
> I seem to remember that Leonardo Spectrum could understand an implicit
> state machine coding style which had multiple wait statements in a
> single process.
>
> But I haven't tried that out recently with modern tools. I always tell
> people on training courses to only use one wait in a synthesisable
> process
>
> regards
> Alan
>

Even if a process has more than one wait, it cannot synthesize
with any tool I'm aware of unless all waits are on the same
event, for example rising_edge(clk). And many synthesizers
are more restrictive than that.

-- Gabor

Martin Thompson
Guest
Posts: n/a

 01-25-2013
Alan Fitch <(E-Mail Removed)> writes:

> On 22/01/13 20:04, valtih1978 wrote:
>> > a wait statement

>>
>> Wait. My teacher taught me that "a" means "one" in English. And, this is
>> what all synthesizers want in VHDL -- one and only one wait.
>>

>
> I don't think that's completely true.
>
> I seem to remember that Leonardo Spectrum could understand an implicit
> state machine coding style which had multiple wait statements in a
> single process.

Like this

http://parallelpoints.com/inferred-s...of-all-things/

Cheers,
Martin

--
http://www.velocityreviews.com/forums/(E-Mail Removed)
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities...ronic-hardware

Tricky
Guest
Posts: n/a

 01-25-2013
On Wednesday, 23 January 2013 01:03:39 UTC, rickman wrote:
> On 1/22/2013 11:56 AM, Andy wrote:
>
> > On Monday, January 21, 2013 1:57:43 PM UTC-6, rickman wrote:

>
> >> On 1/21/2013 1:51 PM, GaborSzakacs wrote:> Karol Hennessy wrote:>> I'm currently trying to work through some examples in one of Pong>> Chu's books. There's one thing I'm not quite clear on. In many of his>> examples he uses lots of if .. else statements, but hardly ever for>> loops. In some of the questions, you're asked to extend some example>> he has given, e.g. going from say 4bit input to 12bit or something>> like that.>> >> Forthis kind of example, it seems natural to me to use some sort of>> loop for each of the 12bits. Is this poor practice?>> >> One example he gives is a priority encoder, where you output the>> highest bit that is set to 1.If we have 4 bit input and 3 bit output,>> we would have>> >> in out "1XXX" "100" (4)>> "01XX" "011" (3)>> "001X" "010" (2)>> "0001" "001" (1)>> "0000" "000" (0)>> >> If we had some 32bit input std_logic_vector, would we really have to>> explicitly code each case or is there some sort of looping we can use?>> W

>
> hat is the preferred method to deal with long std_logic_vectors?> > Loops are a perfectly valid way to implement a priority encoder. Often> textbooks are very behind the curve in synthesis technology, and it> wasn't that long ago that many synthesis tools had poor if any> support for loops. Also it is generally not a good idea for beginners> to start thinking in terms of loops until they have an understanding> of the potentially large hardware that a loop creates when it gets> unrolled.> > I'm most familiar with Xilinx tools, where there are some strict> restriction on loops, especially that the number of iterations> must be a constant at synthesis time.. So in the case of a 32-bit> priority encode, your loop for simulation would probably work> best if it is coded to exit as soon as the first '1' bit is> found. But for synthesis, at least for XST, you'd code it with> a variable to remember that the first one has already been found and> an if statement to prevent furth
>
> er assignments on the remining> loop iterations. I've been coding in VHDL for some 15+ years and I can't remember using loops for synthesized code once. But I think a priority encoder would be a perfect use of a loop. I would loop from the lowest priority bit to the highest priority bit and overwrite the variable with the corresponding bit number each time it is a one. At the end of the loop the variable is set to the right value and can be assigned to a signal. BTW, do you plan to have a separate signal to indicate the presence of a 1 bit in the word or will you use a zero code for no bitsset and use a 1 based count for the msb bit position requiring a 6 bit priority word? I would code this unit separately and test it in synthesis to see what is produced. It should produce the priority chain of gates or more likely optimize it to something not so easily recognizable. But it would beinteresting to see if it is reasonably efficient. At 32 bits a priority encoder can be pretty messy
>
> . Rick
>
> >

>
> > If you are not comfortable or familiar with using loops in synthesis, Istronly agree that caution is necessary.

>
> >

>
> > IMHO, most university courseware for HDL based design does a miserable job of covering basic SW techniques that are fully applicable to HW design.So unless one snoops around on their own, purchases the right book, or gets advanced training, they are unlikely to understand or use these techniques. That is not to say that you can't design reliable HW without these techniques, but it is much harder to develop maintainable, reliable designs without them.

>
> ...snip...
>
> >

>
> > Andy

>
>
>
> I never said I was "not comfortable" or familiar with using loops in
>
> synthesis. I said I hadn't used one that I can recall, meaning I've
>
> found little need. I don't recall ever coding a priority encoder which
>
> is one function that can be easily with a loop. Otherwise I can't think
>
> of any functions that are easier or better described with a loop.
>
>
>
> Can you give some common examples of loops in synthesis?
>
>
>
> Rick

Mult-adder trees where the input sizes are a generic would be an easy one for loops. But you could move them to generate loops (But IMO, the loops inside a process would be tidier because you dont need the extra signals for the reigsters).

And being pedantic, all of the numeric_std arithmatic, and the reduction oporators in std_logic_misc all use for loops.