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time to digital convertor

 
 
BLue39
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      12-25-2012
I need to find the difference between two signal's arrival time with the resolution of 200 ps.
I'm using Virtex-6 XC6VLX240T-ff1156-1.

I think I'll be required to build a TDC.

Can anyone help me about how to start that?

--BLue39
 
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Allan Herriman
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      12-25-2012
On Tue, 25 Dec 2012 04:02:10 -0800, BLue39 wrote:

> I need to find the difference between two signal's arrival time with the
> resolution of 200 ps.
> I'm using Virtex-6 XC6VLX240T-ff1156-1.
>
> I think I'll be required to build a TDC.
>
> Can anyone help me about how to start that?
>
> --BLue39



There are many ways to build a time-to-digital converer (TDC). Many of
them require lots of analog circuitry, but this is a VHDL newsgroup and
you want to use an FPGA, so here's a completely digital approach:

Virtex-6 *LXT-1 has GTX transceivers that will work at 5Gb/s.

You can put them in "lock to reference" mode that disables the CDR and
can be used to sample the input signals at 5Gb/s.

You'll need to disable every feature in the transceiver that causes
latency to be variable or unknown (the Elastic Buffer in particular).
Either that, or use some sort of external calibration to null out the
latency difference between the two transceivers.

The output of the transceivers (inside the FPGA fabric) will be a
parallel bus at a much lower clock frequency, e.g. a 20 bit wide datapath
clocked at 250MHz or a 16 bit datapath clocked at 312.5MHz.

It should be fairly easy for you to create logic that decodes the bus
contents to locate the transistions caused by each signal's arrival time,
then computes the difference.


If you have problems getting logic to work at 312.5MHz, try adding a
small circuit to change the bus to twice the width at half the clock
frequency, e.g. 32 bit at 156.25MHz.


Regards,
Allan
 
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BLue39
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Posts: n/a
 
      01-04-2013
Hi ALAN,

Thanx for the reply.
I have never worked with GTX transceivers, but the approach you have suggested seems quite efficient.

I'll try to develop a code which implements you idea.

If I'll get stuck at some point, I'll contact you.

Thanks man


> There are many ways to build a time-to-digital converer (TDC). Many of
>
> them require lots of analog circuitry, but this is a VHDL newsgroup and
>
> you want to use an FPGA, so here's a completely digital approach:
>
>
>
> Virtex-6 *LXT-1 has GTX transceivers that will work at 5Gb/s.
>
>
>
> You can put them in "lock to reference" mode that disables the CDR and
>
> can be used to sample the input signals at 5Gb/s.
>
>
>
> You'll need to disable every feature in the transceiver that causes
>
> latency to be variable or unknown (the Elastic Buffer in particular).
>
> Either that, or use some sort of external calibration to null out the
>
> latency difference between the two transceivers.
>
>
>
> The output of the transceivers (inside the FPGA fabric) will be a
>
> parallel bus at a much lower clock frequency, e.g. a 20 bit wide datapath
>
> clocked at 250MHz or a 16 bit datapath clocked at 312.5MHz.
>
>
>
> It should be fairly easy for you to create logic that decodes the bus
>
> contents to locate the transistions caused by each signal's arrival time,
>
> then computes the difference.
>
>
>
>
>
> If you have problems getting logic to work at 312.5MHz, try adding a
>
> small circuit to change the bus to twice the width at half the clock
>
> frequency, e.g. 32 bit at 156.25MHz.
>
>
>
>
>
> Regards,
>
> Allan


 
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Allan Herriman
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Posts: n/a
 
      01-04-2013
On Thu, 03 Jan 2013 22:56:18 -0800, BLue39 wrote:

> Hi ALAN,
>
> Thanx for the reply.
> I have never worked with GTX transceivers, but the approach you have
> suggested seems quite efficient.
>
> I'll try to develop a code which implements you idea.
>
> If I'll get stuck at some point, I'll contact you.
>
> Thanks man



Try reading this Xilinx Answer Record first:
http://www.xilinx.com/support/answers/38550.htm

It explains how to enable "lock to reference" mode for the GTX in Virtex
6.

Regards,
Allan
 
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