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What does 'SnKDone' signal stand for?

 
 
fl
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      12-02-2012
Hi,

I use Matlab HDL Coder to generate VHDL code for my project. I am new to VHDL. One of the test signals is 'SnKDone'. I guess this signal name can tellsome the significant of the test purpose and it may be used by some VHDL programmer. Do you know what meaning it is?

Thanks,
 
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Rob Gaddi
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      12-03-2012
On Sun, 2 Dec 2012 12:35:03 -0800 (PST)
fl <(E-Mail Removed)> wrote:

> Hi,
>
> I use Matlab HDL Coder to generate VHDL code for my project. I am new to VHDL. One of the test signals is 'SnKDone'. I guess this signal name can tell some the significant of the test purpose and it may be used by some VHDL programmer. Do you know what meaning it is?
>
> Thanks,


Short for snack done. You assert it to flag to the process that you're back from your lunch break.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.
 
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Andy
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      12-03-2012

That's only in slave mode. In master mode, it is an output telling you thatthe FPGA is through with its snack. If it wants another snack, it asserts SnKReq, and then you assert SnKRsp, and then it asserts SnKAck. Then when it's done, it asserts SnKDone again.

I would get rid of this product. It's bad enough my dog wants a snack everytime I have one, but now my FPGA too?!

Andy
 
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