I have to generate a 78MHz clock (duty cycle 0.5 or 0.7) from a 100MHz base clock (duty cycle 0.5) using VHDL language (so the ratio is 200/156). I know that I can use DCM, PLL or similar, but at this moment (unfortunately) I just can't.
Therefore I thought to use (excluding any DCM or PLL) a simple frequency divider, but in this case I also know that the frequency can be divided only by integer numbers (and minimum 2, because I would use counters to do that  and In my case I have to divide the base clock by 1,2820512820512820512820512820513...).
So I have no idea how to realize that without using any DCM or other stuff... I thought to divide the 100MHz clock in smaller frequencies (like 50MHz, 25MHz etc.) and adding them (50+25+3 for example), but is this the right way (logically I don't think so)?
So, have you some suggests?
