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Can we log internal signals from a testbench in VHDL?

 
 
py
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Posts: n/a
 
      11-20-2012
Hi,

Thanks for the tip. I certainly had tried the LRM naming convention you suggest, and in return, I would see the following Riviera elaboration error:

# ELBREAD: Elaboration time 5.4 [s].
# KERNEL: Main thread initiated.
# KERNEL: Kernel process initialization phase.
# KERNEL: Time resolution set to 1ps.
# ELAB2: Elaboration final pass...
# KERNEL: PLI/VHPI kernel's engine initialization done.
# PLI: Loading library '/usr/local/riviera-pro-2012.02-x86_64/bin/libsystf.so'
# VHPI: Loading library 'systf.so'
# ELAB2: Create instances ...
# ELAB2: Fatal Error: ELAB2_0135 tb.vhd (519): Subtype indication of external name that denotes an unelaborated object is not fully constrained or external name does not exist.
# KERNEL: Error: E8005 : Kernel process initialization failed.
# VSIM: Error: Simulation initialization failed.

The total number of instances generated in the generate statement is set to a constant (and I also tried just force it to a number), so I'm guessing it's not about instances being fully constraint?


Thanks

> The name "py" posted isn't following the LRM. The LRM says the names
>
> will be generated with parantheses e.g.
>
>
>
> gen_module(0).module
>
>
>
> I know that Modelsim changed the way they displayed names in the
>
> hierarchy viewer in a recent version to follow the LRM properly,
>
>
>
> regards
>
> Alan
>
>
>
> --
>
> Alan Fitch

 
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py
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Posts: n/a
 
      11-30-2012
Hi,

Sorry, was busy this week so this reply comes a bit late. The code I tried is

assert(false) report "Maximum FIFO depth: " & to_string(<<signal .tb.dut.gen_sample_reader__0.sample_reader.request _fifo_depth_wr_max : std_logic_vector>>) severity note;
-> fails during compile

assert(false) report "Maximum FIFO depth: " & to_string(<<signal .tb.dut.gen_sample_reader(0).sample_reader.request _fifo_depth_wr_max : std_logic_vector>>) severity note;
-> fails during elaboration

instance_name looks like it could be useful. Is there any quick way to convert the output to a string so that I can display it?

assert(i_req = '0') report "DEBUG: " & to_string(req_fifo_depth_wr_max'instance_name);

VHDL2008 was enabled via the -hdl_version 2008 compile flag.


Thanks!


On Wednesday, 21 November 2012 16:20:01 UTC-8, Alan Fitch wrote:
> On 20/11/12 22:42, py wrote:
>
> > Hi,

>
> >

>
> > Thanks for the tip. I certainly had tried the LRM naming convention you suggest, and in return, I would see the following Riviera elaboration error:

>
> >

>
> > # ELBREAD: Elaboration time 5.4 [s].

>
> > # KERNEL: Main thread initiated.

>
> > # KERNEL: Kernel process initialization phase.

>
> > # KERNEL: Time resolution set to 1ps.

>
> > # ELAB2: Elaboration final pass...

>
> > # KERNEL: PLI/VHPI kernel's engine initialization done.

>
> > # PLI: Loading library '/usr/local/riviera-pro-2012.02-x86_64/bin/libsystf.so'

>
> > # VHPI: Loading library 'systf.so'

>
> > # ELAB2: Create instances ...

>
> > # ELAB2: Fatal Error: ELAB2_0135 tb.vhd (519): Subtype indication of external name that denotes an unelaborated object is not fully constrained or external name does not exist.

>
> > # KERNEL: Error: E8005 : Kernel process initialization failed.

>
> > # VSIM: Error: Simulation initialization failed.

>
> >

>
> > The total number of instances generated in the generate statement is set to a constant (and I also tried just force it to a number), so I'm guessing it's not about instances being fully constraint?

>
> >

>
> Oh.
>
>
>
> Can you post the exact path you typed in to the code?
>
>
>
> Also have you tried using 'instance_name to print out the path?
>
>
>
> Finally (probably a stupid question) have you enabled VHDL-2008 when
>
> compiling?
>
>
>
> regards
>
> Alan
>
>
>
>
>
> --
>
> Alan Fitch


 
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Martin Thompson
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Posts: n/a
 
      11-30-2012
py <(E-Mail Removed)> writes:

> instance_name looks like it could be useful. Is there any quick way to convert
> the output to a string so that I can display it?
>
> assert(i_req = '0') report "DEBUG: " &
> to_string(req_fifo_depth_wr_max'instance_name);
>


I may be missing something, but isn't the instance_name property already
a string?

assert(i_req = '0') report "DEBUG: " & req_fifo_depth_wr_max'instance_name;

should be fine.

--
http://www.velocityreviews.com/forums/(E-Mail Removed)
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities...ronic-hardware
 
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py
Guest
Posts: n/a
 
      12-01-2012
Opps, you are right! Here is the output on the console

tb(struct):dut@module(rtl):gen_sample_reader(0):sa mple_reader@module(rtl):req_fifo_depth_wr_max

so according to this, this should had work right? But Riviera elaboration process complained about it. I guess it is time to email support.

.tb.dut.gen_sample_reader(0).sample_reader.request _fifo_depth_wr_max


On Friday, 30 November 2012 01:49:12 UTC-8, Martin Thompson wrote:
> py <(E-Mail Removed)> writes:
>
>
>
> > instance_name looks like it could be useful. Is there any quick way to convert

>
> > the output to a string so that I can display it?

>
> >

>
> > assert(i_req = '0') report "DEBUG: " &

>
> > to_string(req_fifo_depth_wr_max'instance_name);

>
> >

>
>
>
> I may be missing something, but isn't the instance_name property already
>
> a string?
>
>
>
> assert(i_req = '0') report "DEBUG: " & req_fifo_depth_wr_max'instance_name;
>
>
>
> should be fine.
>
>
>
> --
>
> (E-Mail Removed)
>
> TRW Conekt - Consultancy in Engineering, Knowledge and Technology
>
> http://www.conekt.co.uk/capabilities...ronic-hardware

 
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Jim Lewis
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      12-05-2012
With external names, instance order is important. Make sure to instance the DUT before other testbench code. This will make sure the DUT has been elaborated before you try to access the signal. Aliases in the architecture will be problematic for this same reason.

Good luck,
Jim
 
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py
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      02-20-2013
Sorry for the late update. I ended up contacting Riviera on this issue and it looks like the culprit is a compiler bug. The correct format was shown by the simulator all along

Cheers,
 
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