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Hi,

At the end of a test, I would like to collect some stat in the following manner:

assert false report "Max counter is " & str(counter_value) severity note

This syntax won't work if counter_value is embedded inside DUT and is not a IO port. Is there any way to "peak" inside the inner layer? I heard that for verilog, it is possible to reference internal signal like outer_layer.inner_layer.signal_name


Thanks

Hi py!

> This syntax won't work if counter_value is embedded inside DUT and is not a IO port. Is there any way to "peak" inside the inner layer?

Declare a signal in a package - a "global" signal. Write to this signal
inside your subcomponent, read this signal wherever you want. All you
need is to include this package in all components where you read/write
this signal.

To make this subcomponent synthesizeable use
-- pragma translate_off
.... your problemativ VHDL code here ...
-- pragma translate_off

As an alternative you can use a "shared variable". This can be written
from several locations while the signal should be written only from one
location.

Ralf

On Thursday, November 8, 2012 11:23:29 PM UTC-8, Ralf Hildebrandt wrote:
> Hi py!
>
>
>
> > This syntax won't work if counter_value is embedded inside DUT and is not a IO port. Is there any way to "peak" inside the inner layer?
>
>
>
> Declare a signal in a package - a "global" signal. Write to this signal
>
> inside your subcomponent, read this signal wherever you want. All you
>
> need is to include this package in all components where you read/write
>
> this signal.
>
>
>
> To make this subcomponent synthesizeable use
>
> -- pragma translate_off
>
> ... your problemativ VHDL code here ...
>
> -- pragma translate_off
>
>
>
> As an alternative you can use a "shared variable". This can be written
>
> from several locations while the signal should be written only from one
>
> location.
>
>
>
> Ralf

Wow that's fast, thanks!

Hi,

py wrote:
> Hi,
>
> At the end of a test, I would like to collect some stat in the
> following manner:
>
> assert false report "Max counter is " & str(counter_value) severity
> note
>
> This syntax won't work if counter_value is embedded inside DUT and is
> not a IO port. Is there any way to "peak" inside the inner layer? I
> heard that for verilog, it is possible to reference internal signal
> like outer_layer.inner_layer.signal_name

if you use Modelsim, there's the "modelsim_util" package with functions
for that purpose. You can use it like this:

library modelsim_lib;
use modelsim_lib.util.all;

-- entity, architecture, signal declarations skipped

-----------------------------------------------------------------------------
-- spy process
-----------------------------------------------------------------------------
sig_spy : process is
begin
init_signal_spy("/DUT/submodule1/submodule2/interesting_sig",
"tb_sig", 1);
wait;
end process sig_spy;

Here, you connect a signal from somewhere inside your DUT to another
signal in your test bench and can then use it there for whatever you need.

Also, in VHDL2008 hierarchical references are supported, so you can do
stuff like this (taken from the Modelsim documentation):

REPORT "Test Pin = " & integer'image(<<SIGNAL .tb.dut.i0.tp : natural>>)
SEVERITY note;

The test bench has to be compiled as VHDL2008, obviously (by calling the
compiler with a corresponding option).

This is part of the VHDL2008 standard, so should work with every
simulator that supports it. But at the moment not every tool vendor has
implemented all of VHDL2008, so this specific feature might not be
supported by your simulator.

Greetings,
Sean

Hi Sean,

I tried the hierachical referenece method and ran into an issue. It does work if I could reference a signal in an instantiated module. However, what should the syntax be if a module is generated? ie:

gen_counter : for idx in 0 to max-1 generate

counter: entity work.counter
....
....

end generate gen_counter;

The signal I want to reference inside the counter module.


Thank you


On Friday, 9 November 2012 00:25:30 UTC-8, Sean Durkin wrote:
> Hi, py wrote: > Hi, > > At the end of a test, I would like to collect some stat in the > following manner: > > assert false report "Max counter is "& str(counter_value) severity > note > > This syntax won't work if counter_value is embedded inside DUT and is > not a IO port. Is there any way to "peak" inside the inner layer? I > heard that for verilog, it is possible toreference internal signal > like outer_layer.inner_layer.signal_name if you use Modelsim, there's the "modelsim_util" package with functions for thatpurpose. You can use it like this: library modelsim_lib; use modelsim_lib.util.all; -- entity, architecture, signal declarations skipped ----------------------------------------------------------------------------- -- spy process ----------------------------------------------------------------------------- sig_spy : process is begin init_signal_spy("/DUT/submodule1/submodule2/interesting_sig", "tb_sig", 1); wait; end process sig_spy; Here, you connect a signal from somewhere inside your DUT to another signal in your test bench and can then use it there for whatever you need. Also, in VHDL2008hierarchical references are supported, so you can do stuff like this (taken from the Modelsim documentation): REPORT "Test Pin = " & integer'image(<<SIGNAL .tb.dut.i0.tp : natural>>) SEVERITY note; The test bench has to becompiled as VHDL2008, obviously (by calling the compiler with a corresponding option). This is part of the VHDL2008 standard, so should work with every simulator that supports it. But at the moment not every tool vendor has implemented all of VHDL2008, so this specific feature might not be supported by your simulator. Greetings, Sean

Each counter label will have the generate index appended to it. You should be able to see this in the name of the signal if you trace it.

Andy

py wrote:
> Hi Sean,
>
> I tried the hierachical referenece method and ran into an issue. It
> does work if I could reference a signal in an instantiated module.
> However, what should the syntax be if a module is generated? ie:
>
> gen_counter : for idx in 0 to max-1 generate
>
> counter: entity work.counter ... ...
>
> end generate gen_counter;
>
> The signal I want to reference inside the counter module.

Yeah, I'm always unclear about that, too.

Usually I just click through the hierarchy in the simulator GUI and then
copy&paste the displayed hierarchy name.

HTH,
Sean

Sorry guys, still can't get this to work

TB code:
assert(false) report "Maximum FIFO depth: " & to_string(<<signal .tb.dut.gen_module__0.module.fifo_depth : std_logic_vector>>) severity note;

Copy and Paste from sim environment
sim:/tb/dut/gen_module__0/module/fifo_depth

For some reason, I would get the following compile error from Riviera Pro:

COMP96 ERROR COMP96_0010: "Invalid literal." "../tb.vhd" 675 98
COMP96 ERROR COMP96_0018: "Identifier expected expected." "../tb.vhd" 675 98

The 98th character position is right at the beginning of 'gen_module__0', so it looks like from the compiler's POV, the module is not yet generated.

Note that if I have something other than gen_module__0 in place, then the code would actually compiled, but would then fail at elaboration. So I do think we are moving at the right direction.



On Tuesday, 13 November 2012 03:00:53 UTC-8, Sean Durkin wrote:
> py wrote:
>
> > Hi Sean,
>
> >
>
> > I tried the hierachical referenece method and ran into an issue. It
>
> > does work if I could reference a signal in an instantiated module.
>
> > However, what should the syntax be if a module is generated? ie:
>
> >
>
> > gen_counter : for idx in 0 to max-1 generate
>
> >
>
> > counter: entity work.counter ... ...
>
> >
>
> > end generate gen_counter;
>
> >
>
> > The signal I want to reference inside the counter module.
>
>
>
> Yeah, I'm always unclear about that, too.
>
>
>
> Usually I just click through the hierarchy in the simulator GUI and then
>
> copy&paste the displayed hierarchy name.
>
>
>
> HTH,
>
> Sean

Hi,

py wrote:
> Sorry guys, still can't get this to work
>
> TB code: assert(false) report "Maximum FIFO depth: " &
> to_string(<<signal .tb.dut.gen_module__0.module.fifo_depth :
> std_logic_vector>>) severity note;
>
> Copy and Paste from sim environment
> sim:/tb/dut/gen_module__0/module/fifo_depth
>
> For some reason, I would get the following compile error from Riviera
> Pro:
>
> COMP96 ERROR COMP96_0010: "Invalid literal." "../tb.vhd" 675 98
> COMP96 ERROR COMP96_0018: "Identifier expected expected." "../tb.vhd"
> 675 98
>
> The 98th character position is right at the beginning of
> 'gen_module__0', so it looks like from the compiler's POV, the module
> is not yet generated.
>
> Note that if I have something other than gen_module__0 in place, then
> the code would actually compiled, but would then fail at elaboration.
> So I do think we are moving at the right direction.

hmm, can't help you on that one, I'm afraid. I guess we need one of the
VHDL gurus now...

Is "fifo_depth" an unconstrained std_logic_vector? If not, maybe you
need to specify the actual range for it so the tool can find it. Just
guessing...

Bye,
Sean

On Wednesday, 14 November 2012 04:56:16 UTC-8, Sean Durkin wrote:
> Hi, py wrote: > Sorry guys, still can't get this to work > > TB code: assert(false) report "Maximum FIFO depth: " & > to_string(<<signal .tb.dut.gen_module__0.module.fifo_depth : > std_logic_vector>>) severity note; > > Copy and Paste from sim environment > sim:/tb/dut/gen_module__0/module/fifo_depth > > For some reason, I would get the following compile error from Riviera > Pro: > > COMP96 ERROR COMP96_0010: "Invalid literal." "../tb.vhd" 675 98 > COMP96 ERROR COMP96_0018: "Identifier expected expected." "../tb.vhd" > 675 98 > > The 98th character position is right at the beginning of > 'gen_module__0', so it looks like from the compiler's POV, the module > is not yet generated. > > Note that if I have something other than gen_module__0 in place, then > the code would actually compiled, but would then fail at elaboration. > So I do think we are moving at the right direction. hmm, can't help you on that one, I'm afraid. I guess we need one of the VHDL gurus now... Is "fifo_depth" an unconstrained std_logic_vector? If not, maybe you need to specify the actual range for it so the tool can find it. Justguessing... Bye, Sean


fifo_depth has a fixed range
signal fifo_depth : std_logic_vector(8 downto 0);

Thanks for your time, we are getting there