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On Wednesday, October 17, 2012 11:57:46 AM UTC-5, (E-Mail Removed) wrote:
> Hello, Thanks for your input guys! I am currently using VHDL93 (in order to remain rather compatible with the whole team; plus I did not have much time to venture on my own). Some still believe that VHDL2008 is not well supported etc... (But I guess I would keep that for a different thread). - If am using VHDL93 with ISE 13.2, the "aggregate" of std_logic_vector does notwork, it only works for std_logic types. - 1) The "range" tip and using the "high/low" attributes of the previous range seems to be a good enough approach for me (at least it does not cascade into infinitely long lines). - 2) This does seem more intuitive for some cases. But it happens to be that Iam using a generic fifo (depth and width) and the data ports are of std_logic_vector type. Andy, I do have some questions concerning your 2nd suggestion. - Did you mean, to have the FIFO's ports as records? Or to cast the std_logic_vector into a record in the top-level where the FIFO is instantiated? - The way I see it, to have a rather generic FIFO of records, we would have to declare the record type in an external package and change that according to the design. But then again, my FIFO will no longer be generic enough to be reused differently in the same design (e.g. if I need to use 2 different FIFOs) - Also, I had previously had some trouble inferring block RAM using records (I had to "un-wrap/re-wrap" the record into an std_logic_vector type). Note that I might have been using older tools at the time. C.

You have just hit onto one of the advantages of records on ports. You can use them like an electrical conduit in a building. Route the conduit throughthe walls first, then decide later what wires need to be pulled through the conduit.

Note that the subranges can also make converting between the record and theSLV easier. Just define the record elements with ranges that reflect theirlocation in the corresponding all-in-one SLV.

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