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"Open" banned on procedures - Is this an LRM thing?

 
 
Tricky
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      08-23-2012
So I have the following code:

architecture rtl of play_TB is

procedure proc(signal a,b : out std_logic) is
begin
a <= '1';
b <= '0';
end proc;

signal c : std_logic;

begin

process
begin
proc(open, c);

wait;
end process;

end rtl;

And Modelsim says this:

# ** Error: play_TB.vhd(27): (vcom-1037) Signal formal "a" has OPEN or no actual associated with it.
#
# ** Error: play_TB.vhd(32): VHDL Compiler exiting
# D:/modeltech_pe_10.1c/win32pe/vcom failed.

is this an LRM thing? why can you leave connections to Entities "open" whenyou cant leave procedures open? I have at least one instance where I only need half the signals from a procedure connected, but because of this feature, I have to create dummy signals so the modelsim compiler doesnt complain..
 
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Andy
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      08-25-2012
On Thursday, August 23, 2012 9:26:10 AM UTC-5, Tricky wrote:
> So I have the following code: architecture rtl of play_TB is procedure proc(signal a,b : out std_logic) is begin a <= '1'; b <= '0'; end proc; signal c : std_logic; begin process begin proc(open, c); wait; end process; end rtl; And Modelsim says this: # ** Error: play_TB.vhd(27): (vcom-1037) Signal formal "a" has OPEN or no actual associated with it. # # ** Error: play_TB.vhd(32): VHDL Compiler exiting # D:/modeltech_pe_10.1c/win32pe/vcom failed. is this an LRM thing? why can you leave connections to Entities "open" when you cant leave procedures open? I have at least one instance where I only need half the signals from a procedure connected, but because of this feature, I have to create dummy signals so the modelsim compiler doesnt complain.


Yes, its an "LRM thing".

You only need to create one dummy signal (since it is resolved).

Andy
 
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