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Weng, That is a copyrighted standard, for which you must pay IEEE or
one of their distributors (IHS, et al).

Jim, I was not aware that 1076.6 was deprecated. When/why did that
happen? Did/will something else replace it? The 2004 edition is quite
good at describing the coded behavior necessary to infer a register
and/or latch. Combinatorial processes are assumed to be everything
else.

Andy

Weng Tianxiang wrote:
> The following topic may be one of the longest debate in vhdl group:
> http://groups.google.com/group/comp....torial&lnk=ol&
>
> The debute focus later turns to which is best way to use one
> sequential process or two combinarotial process and sequential
> process.
>
> The most important and strange thing is that I cannot even find the
> word "combinarotial" in VHDL-2002 specification.
>
> I want to grammarly define a combinatorial process which cannot have a
> clock statement in one of my thinking.
>
> process_statement_part ::=
> { sequential_statement }
>
> sequential_statement ::=
> wait_statement
> | assertion_statement
> | report_statement
> | signal_assignment_statement
> | variable_assignment_statement
> | procedure_call_statement
> | if_statement
> | case_statement
> | loop_statement
> | next_statement
> | exit_statement
> | return_statement
> | null_statement
>
> combinatorial_process_statement_part ::=
> { combinatorial_sequential_statement }
>
> combinatorial_sequential_statement ::=
> assertion_statement -- wait_statement is deleted here !!!
> | report_statement
> | signal_assignment_statement
> | variable_assignment_statement
> | procedure_call_statement
> | if_statement
> | case_statement
> | loop_statement
> | next_statement
> | exit_statement
> | return_statement
> | null_statement
>
> Weng

The traditional meaning of "combinatorial" is that the outputs only
depend on the current state of the inputs. i.e. there can be no
saved state within the process. This not only includes constructs
such as edge dependencies or waits, but also any sort of feedback
from the process outputs or internal signals / variables.

-- Gabor

Gabor wrote:
> Weng Tianxiang wrote:
>> The following topic may be one of the longest debate in vhdl group:
>> http://groups.google.com/group/comp....torial&lnk=ol&
>>
>> The debute focus later turns to which is best way to use one
>> sequential process or two combinarotial process and sequential process.
>> The most important and strange thing is that I cannot even find the
>> word "combinarotial" in VHDL-2002 specification.
>> I want to grammarly define a combinatorial process which cannot have a
>> clock statement in one of my thinking.
>> process_statement_part ::= { sequential_statement }
>> sequential_statement ::= wait_statement | assertion_statement |
>> report_statement | signal_assignment_statement |
>> variable_assignment_statement | procedure_call_statement |
>> if_statement | case_statement | loop_statement | next_statement |
>> exit_statement | return_statement | null_statement
>> combinatorial_process_statement_part ::= {
>> combinatorial_sequential_statement }
>> combinatorial_sequential_statement ::= assertion_statement --
>> wait_statement is deleted here !!! | report_statement |
>> signal_assignment_statement | variable_assignment_statement |
>> procedure_call_statement | if_statement | case_statement |
>> loop_statement | next_statement | exit_statement | return_statement |
>> null_statement
>> Weng
>
> The traditional meaning of "combinatorial" is that the outputs only
> depend on the current state of the inputs. i.e. there can be no
> saved state within the process. This not only includes constructs
> such as edge dependencies or waits, but also any sort of feedback
> from the process outputs or internal signals / variables.
>
> -- Gabor

I forgot to add that feedback in the process isn't always obvious
just by looking at the RHS of the equations. Implicit feedback
occurs when you have incomplete state coverage, as in the latch
example. This makes it a bit tougher to prevent sequential logic
from being inferred just by excluding certain types of statements.

-- Gabor

Hi Weng,
You can buy a copy here:
http://www.techstreet.com/standards/...uct_id=1270145

Best,
Jim

> Jim, I was not aware that 1076.6 was deprecated.
It was due for revision in 2009. Since no one stepped up to lead the group, DASC deprecated both it and the corresponding Verilog one.

Largely users did not pay any attention to it and as a result vendors did not completely implement it. It would be nice to reform a group and revise it, however, someone would need to be willing to do the work. They would also need to get the vendors involved. With FPGAs a diverse set of tools inthe FPGA market, perhaps it can get done. At least for attributes, it really needs to get done.