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Check all bits set

 
 
aleksazr@gmail.com
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      06-22-2012
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

signal WRaddr : unsigned(11 downto 0);

if rising_edge(CLK) then
if WRaddr/="111111111111" then
WRaddr <= WRaddr +1;
end if;
end if;

How do I write this so I can easily
change the length of WRaddr?

TIA
 
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Enrik Berkhan
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      06-22-2012
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
>
> signal WRaddr : unsigned(11 downto 0);
>
> if rising_edge(CLK) then
> if WRaddr/="111111111111" then
> WRaddr <= WRaddr +1;
> end if;
> end if;
>
> How do I write this so I can easily
> change the length of WRaddr?


You could use a constant like

constant WRaddr_all_ones: unsigned(WRaddr'range) := (others => '1');

Enrik
 
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Gabor
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      06-22-2012


(E-Mail Removed) wrote:
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
>
> signal WRaddr : unsigned(11 downto 0);
>
> if rising_edge(CLK) then
> if WRaddr/="111111111111" then
> WRaddr <= WRaddr +1;
> end if;
> end if;
>
> How do I write this so I can easily
> change the length of WRaddr?
>
> TIA


how about

if WRaddr /= (others => '1') then
.. . .

-- Gabor
 
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aleksazr@gmail.com
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      06-22-2012
On Friday, June 22, 2012 7:48:25 PM UTC+2, Gabor wrote:
> (E-Mail Removed) wrote:
> > library ieee;
> > use ieee.std_logic_1164.all;
> > use ieee.numeric_std.all;
> >
> > signal WRaddr : unsigned(11 downto 0);
> >
> > if rising_edge(CLK) then
> > if WRaddr/="111111111111" then
> > WRaddr <= WRaddr +1;
> > end if;
> > end if;
> >
> > How do I write this so I can easily
> > change the length of WRaddr?
> >
> > TIA

>
> how about
>
> if WRaddr /= (others => '1') then
> . . .
>
> -- Gabor


That was my first guess, but ISE 13.3 doesn't like it:
Can not determine the "others" values in aggregate. (LRM 7.3.2.2)
 
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aleksazr@gmail.com
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      06-22-2012
On Friday, June 22, 2012 7:45:41 PM UTC+2, Enrik Berkhan wrote:
> (E-Mail Removed) wrote:
> > library ieee;
> > use ieee.std_logic_1164.all;
> > use ieee.numeric_std.all;
> >
> > signal WRaddr : unsigned(11 downto 0);
> >
> > if rising_edge(CLK) then
> > if WRaddr/="111111111111" then
> > WRaddr <= WRaddr +1;
> > end if;
> > end if;
> >
> > How do I write this so I can easily
> > change the length of WRaddr?

>
> You could use a constant like
>
> constant WRaddr_all_ones: unsigned(WRaddr'range) := (others => '1');
>
> Enrik


That works, thanks
 
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Gabor
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      06-22-2012
(E-Mail Removed) wrote:
> On Friday, June 22, 2012 7:45:41 PM UTC+2, Enrik Berkhan wrote:
>> (E-Mail Removed) wrote:
>>> library ieee;
>>> use ieee.std_logic_1164.all;
>>> use ieee.numeric_std.all;
>>>
>>> signal WRaddr : unsigned(11 downto 0);
>>>
>>> if rising_edge(CLK) then
>>> if WRaddr/="111111111111" then
>>> WRaddr <= WRaddr +1;
>>> end if;
>>> end if;
>>>
>>> How do I write this so I can easily
>>> change the length of WRaddr?

>> You could use a constant like
>>
>> constant WRaddr_all_ones: unsigned(WRaddr'range) := (others => '1');
>>
>> Enrik

>
> That works, thanks


Good point. I missed the declaration type "unsigned". My
code would have worked for std_logic_vector.

Regards,
Gabor
 
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Nicolas Matringe
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      06-22-2012
Le 22/06/2012 20:14, Gabor a écrit :

> Good point. I missed the declaration type "unsigned". My
> code would have worked for std_logic_vector.


I don't think so. Please give it a try.

Another solution would be

if WRaddr /= (WRaddr'range => '1') then


Nicolas
 
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Andy
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      06-24-2012
On Jun 22, 11:55*am, (E-Mail Removed) wrote:
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
>
> signal WRaddr : unsigned(11 downto 0);
>
> if rising_edge(CLK) then
> * * if WRaddr/="111111111111" then
> * * * * WRaddr <= WRaddr +1;
> * * end if;
> end if;
>
> How do I write this so I can easily
> change the length of WRaddr?
>
> TIA


if WRaddr /= 2**WRaddr'length - 1 then -- unsigned/natural compare

if WRaddr /= unsigned'(WRaddr'range => '1') then

Andy
 
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Jim@synthworks.com
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      06-25-2012
if not(WRaddr) /= 0 then

Jim

P.S.
At one time Synopsys DC (ASIC synthesis) gave an error on
having expressions with 'range, like this (although the
language definitely allows it):
if WRaddr /= (WRaddr'range => '1') then

Anyone try this more recently on DC?
 
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Ralf Hildebrandt
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      06-27-2012
Hi!

> if WRaddr/="111111111111" then


> How do I write this so I can easily
> change the length of WRaddr?


if (signed(WRaddr) /= -1) then -- check if all bits set


I would recommend to add the comment, because if "-1" has no meaning for
the usual behavior of WRaddr this code might confuse a colleague. On the
other hand it is very clear to read and uses only very basic VHDL
features (from Numeric_Std package).

Ralf
 
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