On 06/19/2012 09:49 PM, Rob Gaddi wrote:

> On Tue, 19 Jun 2012 15:02:30 -0400

> Gabor<(E-Mail Removed)> wrote:

>

>>

>> Well I for one think it would be much more useful for the synthesizer to

>> wrap to zero after state 6 so the count matches the range of the signal.

>> Obviously that's not the expected behavior for VHDL, though.

>>

>> -- Gabor

>

> Of course it isn't; integers don't do that either in math or in VHDL.
Integers don't do this, but modulo arithmetic is very well

defined in math. And it has many practical applications

of course.

A language like Ada found this important enough to introduce

modular types, which in VHDL would have looked as follows:

signal counter: mod range 0 to 6;

Note that this is an abstract type in which wrap-around

is defined as a mathematical operation; not just for

powers of 2 and not as a side effect of a representation,

as with signed/unsigned.

What I found interesting is that the Ada design docs

explicitly mention the case of powers of 2 as a possible

compiler optimization. The link with hardware design seems

obvious, and I find it a pity that VHDL seems to have

forgotten to keep track of its Ada foundation.

As I believe modular types are ideal for hardware design,

they have been introduced in the development version of MyHDL:

http://myhdl.org/doku.php/meps:mep-106
--

Jan Decaluwe - Resources bvba -

http://www.jandecaluwe.com
Python as a HDL:

http://www.myhdl.org
VHDL development, the modern way:

http://www.sigasi.com
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