On Tuesday, June 12, 2012 12:57:25 PM UTC+1, hssig wrote:
> Hi,
>
> I am trying to use the VHDL2008 library "numeric_std_unsigned" to
> increment a std_logic_vector by one:
>
> use ieee.numeric_std_unsigned.all;
>
> signal vec : std_logic_vector(15 downto 0) := (others => '0');
>
> vec <= vec + 1 when rising_edge(clk);
>
>
> Now I have in the same VHDL file the following conversion:
>
> constant cIniVec : std_logic_vector(15 downto 0) :=
> std_logic_vector(to_unsigned(1,16));
>
>
> That means that I have to include both libraries:
> use ieee.numeric_std.all;
> use ieee.numeric_std_unsigned.all;
>
> Do I use the packages how nature intended it?
>
> Cheers, hssig
You can do something like this:
my_SLV <= SLV(UNSIGNED(my_SLV) + 1);
where SLV is STD_LOGIC_VECTOR, my_SLV is you vector/signal and then you only need the NUMERIC_STD package. (I think)!
