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error in synthesis in vhdl code...

priyanka24 priyanka24 is offline
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Join Date: Jan 2012
Posts: 4

i have written VHDL code and got simulated correctly.

but getting following error during synthesis::

ERROR:Xst:787 : line 98: Index value <9> is not in Range of array <output_stream>.

what is solution for this plz help me?????
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sridars sridars is offline
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Join Date: Apr 2012
Posts: 1
Hi, You must have created 8 bit array and assigning the value to 9th bit of same array.
post the code if possible
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