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Hello,

does someone have an UART with an fractional baudrate generator ? Or the
baudrate generator stand alone ? I search examples in VHDL.

Regards,

Martin

Martin Maurer wrote:

> does someone have an UART with an fractional baudrate generator ? Or the
> baudrate generator stand alone ? I search examples in VHDL.

Search for the identifier tic_per_bit_c
in the reference design source here:

http://home.comcast.net/~mike_treseler/

-- Mike Treseler

Having found a real lack of general purpose UART models, I wrote my own
in VHDL. They are a bit wasteful, in that the TX and RX units both
generate subtiming, but they were intended to be used separately. (I
have a project with an asymetric number of serial receivers and
transmitters)

You just supply the clock frequency as a generic, and the model
calculates the counter values for you. I've tested it at 24Mhz and
50MHz, but there is no reason you couldn't go higher. The model begins
to break down below about 12MHz, though. (sampling becomes a problem
with the way the dividers are set up.)

The models are designed to use FIFO's, but also provide RTS/CTS
support. Sadly, almost every FPGA board I've seen neglects hardware
flow control, despite using a MAX232 chip, which has the hardware to do
it. The FIFO's guarantee proper operation when flow control isn't an
option.

As for configuration, you supply the baudrate, parity, number of stop
bits, number of data bits on SLV's - which could be supplied by a
control module (which I have not written) that would implement the UART
control registers. Likewise, the models provide single signal error and
interrupt flags.

You might not be interested in the models themselves, but perhaps you
can use the sample rate generator logic. The models can correctly
handle baud rates up to 115k - and with a bit of modification, faster.

Email me at jshamlet<AT>hotmail<DOT>com if you would like a copy of
them.

Martin Maurer skrev:

> Hello,
>
> does someone have an UART with an fractional baudrate generator ? Or the
> baudrate generator stand alone ? I search examples in VHDL.
>
> Regards,
>
> Martin

Hi,

The baudrate generator could be written according to the example below:

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;

Entity brgrx Is
Port(
clk : In Std_logic;
res : In Std_logic;
clkrx : Out Std_logic
);
End brgrx;

Architecture RTL Of brgrx Is

Signal brdiv : unsigned(8 downto 0); -- Counter
Signal iclkrx : std_logic; -- Internal CLKRX
Signal ubrr : unsigned(8 downto 0); -- div ratio
Signal toggle : std_logic; -- 351/352 control

Begin

-- Division control. Divide by 351 or 352 to get an average of 351,5

divctrl : Process (clk,res)
Begin
if res = '1' then
toggle <= '0';
elsif rising_edge(clk) then
if iclkrx = '1' then
toggle <= not toggle;
end if;
end if;
End process divctrl;

ubrr <= TO_UNSIGNED(351,9) when toggle = '1' else TO_UNSIGNED(350,9);


-- Divide by ubrr+1 i.e 351/352

divider : Process (clk,res)
Begin
if res = '1' then
brdiv <= (others => '0');
iclkrx <= '0';
elsif rising_edge(clk) then
if brdiv = ubrr then
brdiv <= (others => '0');
iclkrx <= '1';
else
brdiv <= brdiv + 1;
iclkrx <= '0';
end if;
end if;
End Process divider;

clkrx <= iclkrx;

End RTL;

Its not necessary to use two processes, they may be combined to a
single process. It would also be possible to make the toggle control
more complex, to accomplish an average divisor of e.g 351,25 or 351,75
(if the jitter is acceptable).

/Peter