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How to write a Perl script to analyze the I/O dependency of a Verilog code?

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Hi All
Here is an interesting question:
"Given a combinational circuit, for each primary output, find the
number of primary inputs that this output depends on."

It is easy to do structual analysis for a small-size circuit. But for a
circuit with million gates, we need to find a effecient way.
Now assume a gate-level Verilog code for this circuit is given, I plan
to write a script (e.g., Perl) to scan this Verilog code, then for each
output, trace back to find the primary input on which it depends. But I
am new to both Perl and Verilog.
So could you please give me any suggestion or any script example for
references? or is there other way to address this problem effeceintly?

Thanks very much!

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And also, can Verilog PLI deal with this problem?

Please give me a hint... Thanks!

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