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VHDL - Arbitrary Data Type

vino_TUM vino_TUM is offline
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Join Date: Nov 2011
Location: Munich, Germany
Posts: 3

I am having a problem in VHDL related to Component declaration.

Bit width (a generic) of a port signal of type std_logic_vector is not visible to the module where it is
declared as component and so I am getting a compilation error.

How can I make the bit_width/data_type of the port signal generic while declaration and
refine it during instantiation ?

Thanks in advance ....

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Nader Ilahi Nader Ilahi is offline
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Join Date: Jul 2012
Posts: 2
Hello Vino ,

I need more details to confirm that I have understood you , would you please provide the code
that cause the issue .otherwise when you make an instantiation of a component you shoud instantiate the generic aswell in order to be recognized .

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