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Concatenate bits

 
 
aleksa
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      02-29-2012
constant size : integer := 32;
datain : in std_logic_vector(9 downto 0);
signal request : std_logic_vector(size-1 downto 0);

Now I wish to set "request" to "datain", like this:
request <= "0000000000000000000000" & datain;
(datain to lower bits, all other bits to zero)

How do I write that w/o all those zeros?
It should also work if I later change "size".

Thanks
 
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Paul Uiterlinden
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      02-29-2012
aleksa wrote:

> constant size : integer := 32;
> datain : in std_logic_vector(9 downto 0);
> signal request : std_logic_vector(size-1 downto 0);
>
> Now I wish to set "request" to "datain", like this:
> request <= "0000000000000000000000" & datain;
> (datain to lower bits, all other bits to zero)
>
> How do I write that w/o all those zeros?
> It should also work if I later change "size".
>
> Thanks


This is how you can do that:
request <= (1 TO request'LENGTH-datain'LENGTH => '0') & datain;

Or, if the signal assignment is in sequential code (process, procedure), you
can do:

request <= (OTHERS => '0');
request(datain'RANGE) <= datain;

The first assignment sets all bits to zero, while the second assignment
overwrites bits 9..0 with datain. With sequential signal assignments, the
last one wins.

--
Paul Uiterlinden
www.aimvalley.nl
 
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Brian Drummond
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      02-29-2012
On Wed, 29 Feb 2012 04:04:50 -0800, aleksa wrote:

> constant size : integer := 32;
> datain : in std_logic_vector(9 downto 0);
> signal request : std_logic_vector(size-1 downto 0);
>
> Now I wish to set "request" to "datain", like this:
> request <= "0000000000000000000000" & datain;
> How do I write that w/o all those zeros?


-- Given the declarations above,
request <= (size - 1 downto 10 => '0') & datain;
-- would work, but a less accident-prone way is
request <= (size - 1 downto datain'length => '0') & datain;
-- or even
request <= (request'high downto datain'length => '0') & datain;
-- Brian
 
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