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truncating std_logic_vector multiplication result question

vivo_m vivo_m is offline
Junior Member
Join Date: Feb 2012
Posts: 3
I want to multiply two std_logic_vector(7 downto 0),but i want the result to be std_logic_vector(7 downto 0) not std_logic_vector(15 downto 0)..
is there any idea how can i do this??
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joris joris is offline
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Join Date: Jan 2009
Posts: 152
I think you can simply have,
variable x, y : unsigned(7 downto 0);
variable z : unsigned(7 downto 0);

z := x * y; -- drops 8 most significant bits
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