This release simplifies configuration of generated tests.
* Generated runners now have a SIMULATOR_INCLUDES array
, whose entries specify places where Verilog source files,
needed by the Verilog design, reside.
* Generated Verilog benches now inherit all `include and
`define directives from the Verilog design in a simpler
* A generated test no longer requires its Verilog design
to reside in the same directory.
* The sample tests have been updated accordingly.