On Jan 24, 10:43*pm, James Kuyper <(E-Mail Removed)> wrote:

>

> The case that I'm most familiar with, IEEE 754 double precision,

> sub-normal numbers have an exponent of 0,

> Within this scheme, could you provide an example of the "many possible

> representations for each number" that you're referring to?

>
IEEE denormalised numbers have an exponent of 0 (represents 2^-1023),

but no implicit leading set bit. So very small numbers can be

represented.

Now imagine that instead of an implict set bit, we have a real bit,

which can be toggled on or off, and a floating exponent. Now we can

represent very many numbers in several ways. We can shift the mantissa

right, clear the leading bit, and increment the exponent by one,

without changing the value, assuming that the lost low bit of the

mantissa was clear.

So my question was, how to do efficent tests for equality, on such an

architecture?

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