I am currently attempting to use the following TCL script to control the simulation flow of my DUT. It basically does the following:
Reads in a txt file to get individual test names, passes each individual test name to the testbench framework. The idea being that each test is performed under a separate vsim command as opposed to having them concatenated together in one simulation run. I extract the system time at the start and end of each simulation run to pass into a log file. The first system time is passed in as a generic, the final system time is passed in as a force command when I encounter a pre-set breakpoint towards the end of the sim.
When my testbench eventually completes a simulation, it finishes with the following statement:
assert not(V_FINISH) report "Test Complete " severity failure;
The problem that I am having is that when the above line is executed, control is not passed back to the TCL file (which makes sense I guess as I’ve killed the simulation run). Is there a way of cleanly passing control back to the TCL script to get it to continue around the loop?
while { [gets $infile line] >= 0 } {
set length [string length $line]
if {[lsearch $line --* ] == -1} {
if {$length != 0} {
#Set the simulation time string
set str [clock format [clock seconds]]
#Vsim command and dereferenced tcl variable passed in as generic for time & date & test name
vsim -onfinish exit -G/uart_tb/u_uart_tb_control/time_string=\"$str" -G/uart_tb/u_uart_tb_control/g_test_name=\"$line" work.uart_tb
#Set the breakpoints for time insertion
bp ../testbench/UART_TB_CONTROL.vhd 415
# Set the commands that get executed when we encounter the breakpoints
# Capture the system time
# force the string value set in the design with this value
# continue the simulation
onbreak {set str [clock format [clock seconds]]; force -freeze sim:/uart_tb/U_UART_TB_CONTROL/FINAL_TIME $str 0; run -continue }
do wave.do
run -all
}
}
}
Many thanks.
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