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Hello,

I've recently downloaded some VHDL code
(http://www.xess.com/projects/sdramtst-1_6.zip), and I would like to
port this code to run on an Altera FPGA.

However, the VHDL code makes reference to the UNISIM library. I am
wondering if it would be possible to modify this code so that it can run
on an Altera processor. What functionality is offered by the UNISIM
library, and is it possible to replicate this functionality using Xilinx
tools?

Thank you,

Nicholas

On 2 Dez., 01:51, Nicholas Kinar <n.ki...@usask.ca> wrote:
> Hello,
>
> I've recently downloaded some VHDL code
> (http://www.xess.com/projects/sdramtst-1_6.zip), and I would like to
> port this code to run on an Altera FPGA.
>
> However, the VHDL code makes reference to the UNISIM library. *I am
> wondering if it would be possible to modify this code so that it can run
> on an Altera processor. *What functionality is offered by the UNISIM
> library, and is it possible to replicate this functionality using Xilinx
> tools?
>
> Thank you,
>
> Nicholas

Hi Nicholas,
UNISIM mainly contains primitive elements of the XILINX FPGAs, but
this may also include special I/O elements and even stuff like DCMs
etc.

Browse the code to find what elements from UNISIM are instantiated.
In most cases (like for AND2 etc.) you will find simple replacements
in the Altera libraries.
For other stuff you have to find something that comes close and adapt
the design, since some elements are specific for each vendors FPGA
fabric.

Have a nice synthesis
Eilert

> Hi Nicholas,
> UNISIM mainly contains primitive elements of the XILINX FPGAs, but
> this may also include special I/O elements and even stuff like DCMs
> etc.
>
> Browse the code to find what elements from UNISIM are instantiated.
> In most cases (like for AND2 etc.) you will find simple replacements
> in the Altera libraries.
> For other stuff you have to find something that comes close and adapt
> the design, since some elements are specific for each vendors FPGA
> fabric.
>
> Have a nice synthesis
> Eilert


Thanks, Eilert; this is very much appreciated! By removing "UNISIM"
from "library IEEE, UNISIM;" I was able to see errors caused by not
having the UNISIM library available.

Most of these errors seem to be associated with not having the
following functions available:

log2
int_select

as well as the following identifiers:

YES
NO

It appears that log2 is the logarithm to the base 2. Alternately,
int_select appears to be something that selects between integers. YES
and NO might map to boolean values.

Is there any VHDL source or documentation available for log2, the
init_select, and the YES and NO values?

Nicholas

On Dec 2, 2:45*pm, Nicholas Kinar <n.ki...@usask.ca> wrote:
> > Hi Nicholas,
> > UNISIM mainly contains primitive elements of the XILINX FPGAs, but
> > this may also include special I/O elements and even stuff like DCMs
> > etc.
>
> > Browse the code to find what elements from UNISIM are instantiated.
> > In most cases (like for AND2 etc.) you will find simple replacements
> > in the Altera libraries.
> > For other stuff you have to find something that comes close and adapt
> > the design, since some elements are specific for each vendors FPGA
> > fabric.
>
> > Have a nice synthesis
> > * *Eilert
>
> Thanks, Eilert; this is very much appreciated! *By removing "UNISIM"
> from "library IEEE, UNISIM;" I was able to see errors caused by not
> having the UNISIM library available.
>
> Most of these errors seem to be associated with not having the
> following functions available:
>
> log2
> int_select
>
> as well as the following identifiers:
>
> YES
> NO
>
> It appears that log2 is the logarithm to the base 2. *Alternately,
> int_select appears to be something that selects between integers. YES
> and NO might map to boolean values.
>
> Is there any VHDL source or documentation available for log2, the
> init_select, and the YES and NO values?
>
> Nicholas

If you have a copy of modelsim with the unisim libraries, see if you
can view the source code here. It is Xilinx Proprietary so you may not
have the source.
As for log2, its a fairly universal function you can write easily with
a for loop:

function log2( i : natural) return integer is
variable temp : integer := i;
variable ret_val : integer := 1; --log2 of 0 should equal 1 because
you still need 1 bit to represent 0
begin
while temp > 1 loop
ret_val := ret_val + 1;
temp := temp / 2;
end loop;

return ret_val;
end function;

On Dec 1, 6:51*pm, Nicholas Kinar <n.ki...@usask.ca> wrote:
> Hello,
>
> I've recently downloaded some VHDL code
> (http://www.xess.com/projects/sdramtst-1_6.zip), and I would like to
> port this code to run on an Altera FPGA.
>
> However, the VHDL code makes reference to the UNISIM library. *I am
> wondering if it would be possible to modify this code so that it can run
> on an Altera processor. *What functionality is offered by the UNISIM
> library, and is it possible to replicate this functionality using Xilinx
> tools?
>
> Thank you,
>
> Nicholas

Check the licensing restrictions on the unisim library and for any
other code from Xilinx. Most I've seen restricts use to Xilinx FPGAs
only.

Andy

On 05/12/2011 10:26 AM, Andy wrote:
>
> Check the licensing restrictions on the unisim library and for any
> other code from Xilinx. Most I've seen restricts use to Xilinx FPGAs
> only.
>
> Andy

Thank you; I will check this out.

Nicholas

>
> If you have a copy of modelsim with the unisim libraries, see if you
> can view the source code here. It is Xilinx Proprietary so you may not
> have the source.
> As for log2, its a fairly universal function you can write easily with
> a for loop:
>
> function log2( i : natural) return integer is
> variable temp : integer := i;
> variable ret_val : integer := 1; --log2 of 0 should equal 1 because
> you still need 1 bit to represent 0
> begin
> while temp> 1 loop
> ret_val := ret_val + 1;
> temp := temp / 2;
> end loop;
>
> return ret_val;
> end function;

Thank you; this is very useful.

Nicholas

On Dec 5, 4:28*am, Tricky <trickyh...@gmail.com> wrote:
> If you have a copy of modelsim with the unisim libraries, see if you
> can view the source code here. It is Xilinx Proprietary so you may not
> have the source.
> As for log2, its a fairly universal function you can write easily with
> a for loop:
>
> function log2( i : natural) return integer is
> * variable temp * *: integer := i;
> * variable ret_val : integer := 1; --log2 of 0 should equal 1 because
> you still need 1 bit to represent 0
> begin
> * while temp > 1 loop
> * * ret_val := ret_val + 1;
> * * temp * *:= temp / 2;
> * end loop;
>
> * return ret_val;
> end function;- Hide quoted text -
>
> - Show quoted text -

This really should not be called log2() because it does not return the
base 2 logarithm of the argument. It returns log2(i) + 1 instead. For
example, log2(1) = 0, log2(2) = 1 and log2(0) is undefined.

-- this (untested) function returns the base 2 logarithm of nn >= 1)
function log2(n : positive) return natural is
variable temp : positive := n;
variable retval : natural := 0;
begin
while temp > 1 loop
retval := retval + 1;
temp := temp / 2;
end loop;
return retval;
end function log2;

I don't know if Xilinx's unisim log2() is similarly mathematically
flawed, but I wanted to make sure that someone googling for a
mathematical function "vhdl log2()" is not mislead. You can probably
tell from the context of how Xilinx uses it whether or not their's is
mathematically accurate, or just logically convenient.

When calculating the number of bits required to represent the range 0
to n, use log2(n) + 1. However, the upper index of an appropriately
sized unsigned subtype would be log2(n), assuming the lower index is
0.

subtype n_range is natural range 0 to n;
subtype n_unsigned is unsigned(log2(n_range'high) downto 0);

variable x : natural range 0 to 0; -- is a constant

Andy

> This really should not be called log2() because it does not return the
> base 2 logarithm of the argument. It returns log2(i) + 1 instead. For
> example, log2(1) = 0, log2(2) = 1 and log2(0) is undefined.
>
> -- this (untested) function returns the base 2 logarithm of nn>= 1)
> function log2(n : positive) return natural is
> variable temp : positive := n;
> variable retval : natural := 0;
> begin
> while temp> 1 loop
> retval := retval + 1;
> temp := temp / 2;
> end loop;
> return retval;
> end function log2;
>
> I don't know if Xilinx's unisim log2() is similarly mathematically
> flawed, but I wanted to make sure that someone googling for a
> mathematical function "vhdl log2()" is not mislead. You can probably
> tell from the context of how Xilinx uses it whether or not their's is
> mathematically accurate, or just logically convenient.
>
> When calculating the number of bits required to represent the range 0
> to n, use log2(n) + 1. However, the upper index of an appropriately
> sized unsigned subtype would be log2(n), assuming the lower index is
> 0.
>
> subtype n_range is natural range 0 to n;
> subtype n_unsigned is unsigned(log2(n_range'high) downto 0);
>
> variable x : natural range 0 to 0; -- is a constant
>
> Andy


Thanks, Andy; this is very helpful. I have now created a VHDL library
with the log2 code.

So this now takes care of the log2 function.

My next step in porting the code is to fix errors related to unknown
identifiers "int_select" as well as "yes" and "no". I am assuming that
these are also defined in the UNISIM library?

Nicholas

On 10/12/2011 12:01 PM, Nicholas Kinar wrote:
>
> My next step in porting the code is to fix errors related to unknown
> identifiers "int_select" as well as "yes" and "no". I am assuming that
> these are also defined in the UNISIM library?
>
> Nicholas
>
>

It turns out that "int_select" is a function in the common.vhd file
distributed with the SDRAM controller code. "Yes" and "No" are simply
constants in the common package found within the common.vhd file. This
seems to complete the final piece of the puzzle.

Nicholas