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[traxfern]

Hey guys this my first time posting here. I'm a beginner at VHDL hoping to have some questions clarified.

I just had a curious question regarding case statements how would I go about setting a two conditional case statement?

process(cond1, cond2)
begin
case (cond1, cond2) is
when (cond1 = xx1) and (cond2 = xx2) => ??? would this work?
etc
.
.
.



Also a second question, say I have a very long IF statement. That checks for one variable for multiple conditions. Is there an efficient way to extend the IF statements to check a second variable without reusing the condition statements again?

For example:

if ( (DrawX = row1) and (DrawY = col2)) then --row1 2 points
G_state <= s1;
break;
elsif ( (DrawX = row1) and (DrawY = col7)) then
G_state <= s2;
break;
elsif ( (DrawX = row2) and (DrawY = col1)) then --row2 8 points
G_state <= s3;
break;
elsif ( (DrawX = row2) and (DrawY = col2)) then
G_state <= s4;
break;

.
.
.

And so on, this goes on for a while. So what I want to do is exchange DrawX with another variable to check say DrawX2. And I don't want to have to rehash the long winded if statements.

thanks