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Counter with initial value

 
 
Obtice Obtice is offline
Junior Member
Join Date: Nov 2011
Posts: 9
 
      11-21-2011
Hi,
I have a counter written in VHDL :

Code:
Library IEEE;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;

Entity counter is
    port
    (
        clk        : in std_logic;
        reset    : in std_logic;
        enable     : in std_logic;
        q        : out integer range 0 to 255
    );
end counter;
Architecture count of counter is
begin
    process (clk)
        variable   cnt    : integer range 0 to 255;
    begin
        if (rising_edge(clk)) then
            if reset = '1' then
                cnt := 0;
            elsif enable = '1' then
                cnt := cnt + 1;
            end if;
        end if;
        q <= cnt;
    end process;
end count;
How can I edit this code, so that it starts to count from 50,
50, 51, 52,53 ......

thanks in advance ....
 
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eliascm eliascm is offline
Member
Join Date: Jan 2009
Posts: 42
 
      11-21-2011
You have a number of options to accomplish this; among these are:

You can set the count to 50 instead of 0 on reset.

You can have a new load input that sets the count to 50 when asserted.
 
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Obtice Obtice is offline
Junior Member
Join Date: Nov 2011
Posts: 9
 
      11-21-2011
thanks,
first solution worked,

Code:
Library IEEE;
use ieee.std_logic_1164.all;

Entity counter is
    port
    (
        clk        : in std_logic;
        reset    : in std_logic;
        enable     : in std_logic;
        q        : out integer range 0 to 255
    );
end counter;
Architecture count of counter is
begin
    process (clk)
        variable   cnt    : integer range 0 to 255;
    begin
        if (rising_edge(clk)) then
            if reset = '1' then
                cnt := 50;
            elsif enable = '1' then
                cnt := cnt + 1;
            end if;
        end if;
        q <= cnt;
    end process;
end count;
but about the second. A bit more tips .... please .
 
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joris joris is offline
Senior Member
Join Date: Jan 2009
Posts: 152
 
      11-24-2011
I think the second option would look similar to this:
Code:
Library IEEE;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;

Entity counter is
    port
    (
        clk        : in std_logic;
        reset    : in std_logic;
        enable     : in std_logic;
        load : in std_logic;
        p: in integer  range 0 to 255
        q        : out integer range 0 to 255
    );
end counter;
Architecture count of counter is
begin
    process (clk)
        variable   cnt    : integer range 0 to 255;
    begin
        if (rising_edge(clk)) then
            if reset = '1' then
                cnt := 50;
            elsif enable = '1' then
                if load = '1' then
                  cnt := p;
                else
                cnt := cnt + 1;
                end if;
            end if;
        end if;
        q <= cnt;
    end process;
end count;
 
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