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error using aggregates in port map

 
 
robstalker robstalker is offline
Junior Member
Join Date: Nov 2011
Posts: 1
 
      11-15-2011
Hi all,

my code looks something like this:

entity lower_block is
generic (
N: integer := 16
);
port (
data_p : inout std_logic_vector(N-1 downto 0);
data_n : inout std_logic_vector(N-1 downto 0);
clock_p : inout std_logic;
clock_n : inout std_logic
);
end lower_block;

entity my_block is
port (
sig_p : inout std_logic_vector(19 downto 0);
sig_n : inout std_logic_vector(19 downto 0)
);
end entity my_block;

architecture rtl of my_block is
begin
my_inst : entity work.lower_block
generic map (N => 9
) port map (
data_p => (6 downto 0 => sig_p(6 downto 0), 8 downto 7 => sig_p(9 downto 0),
data_n => (6 downto 0 => sig_n(6 downto 0), 8 downto 7 => sig_n(9 downto 0),
clock_p => sig_p(7),
clock_n => sig_n(7),
);
end architecture rtl;

I get the following error in Modelsim SE 6.6d:
# ** Warning: ../my_block.vhd(159): Actual expression in port association 9 is not static.
# ** Warning: ../my_block.vhd(160): Actual expression in port association 10 is not static.
# ** Error: ../my_block.vhd(159): Actual (aggregate) for formal "data_p" is not a static signal name.
# ** Error: ../my_block.vhd(160): Actual (aggregate) for formal "data_n" is not a static signal name.

Any ideas?
thanks for your help in advance.
 
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