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PHDL a new HDL for PCB design

 
 
self
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      11-20-2011
KJ

The idea of textual PCB design entry is a small paradigm shift and a
lot of people react emotionally so thanks for your comments.

Everybody I know uses VHDL or Verilog for even very simple CPLD
designs. Of course, for large FPGA's and ASIC design HDL is the
preferred entry method for now.

On board design, I also thought that the analog portions of board
design were best done with schematics, till I tried PHDL. Now I find
that the ability to mix lines of comments with lines of design text
actually makes PHDL more expressive than proprietary schematic entry
methods, even for analog circuits.

Also, at least for the kinds of board I do, PCB design is getting
simpler over time. What used to require a board full of ECL logic now
easily runs inside a low cost FPGA. Switching regulators used to be
quite a challenge to capture. These days, I always use an integrate
controller that usually includes the power FET and often includes the
required inductor as well. It only takes a few lines of PHDL (plus
comments) to capture a switching regulator design.

You are right, I don't have any hard data on productivity but I have
been using schematic entry for over twenty years and now I have done
several designs in PHDL. My subjective impression is that PHDL is
faster, more accurate, more readable and less annoying than
proprietary graphical schematic tools. I use the Vim text editor and
we wrote a sytax highlighter control file for Vim that makes PHDL
design entry really pleasant. When working with schematic entry tools
I keep track of how much time I spend on non-productive tool fiddling
and how much on actual design entry. I think it is 90% fiddling and
10% actual work. In PHDL, I feel the ratio is reversed, 10% fiddling
and 90% design entry.

With respect to efficiency, I find that pure text PHDL design entry
actually requres less typing than the schematic editor that I normally
use (Mentor DxDesigner). I find most of the text can be autogenerated
(FPGA) or cut and pasted from the pdf data sheet. I find the
reduction of typing (and fiddling) really reduces my error rate and
lets me focus on the actual design. Again, this is just an objective
observation. Let me know what you think after you have tried PHDL.

Searching for components by refdes is something that is very unwieldy
in most schematic editor tools. Of course, searching for text within
a text file like PHDL source is very natural. The PHDL compiler
controls the mapping between design pathname and refdes in an open CSV
format file that can be searched to quickly locate any refdes within
the design hierarchy. Furthermore, we are extending the funtionality
of the refdes idea to contain some hierarchical information. This
makes it really easy, in the layout tool, to quickly select all the
components in one part of the design. As far as I know, this is a very
simple but valuable improvement over how schematics usually handle
refdes.

With respect to version control, diff'ing the source design is much
better than diff'ing the machine generated netlist output.

I have actually tried almost all of the graphical logic generation
tools to supposedly improve designer productivity, Xilinx DSP System
Generator, Altera DSP Builder, Aldec BDE block diagram editor,
National Instruments Labview FPGA,... For production designs I always
use strait HDL entry for maintainability. How many proprietary tools
do you want to pay maintenance on just to be able to edit your own
design? PHDL is free and open. You could actually archive the PHDL
compiler (jar file) along with your design for infinite
maintainability.

I am getting together with the compiler designers tomorrow. We are
going to talk about new features for version 2 two of PHDL. The new
features will definitely include

1) Hierarchical design - for modularity. Once we have this, PHDL won't
be linear text but, instead, organized functionally.
2) VHDL output - for design analysis, simulation and graphical
viewing. This is an easy way to get pictures out of your PHDL design.
3) Altium netlist output - Altium is coming on in popularity. People
request Altium netlist format more than any other.
4) Record Type nets - We want to do this better and simpler than VHDL.
Ie., we want to be able to combine inputs and outputs in a single
record.
5) Full parser re-write - The guys want to do a little "refactoring"
now that they have written a compiler and are a lot smarter.

Once again, thanks for the comments and ideas. The very fact that you
guys are participating on this use group means you are looking for new
ideas. Maybe PHDL is not for you.

Best wishes,

Pedro


 
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self
Guest
Posts: n/a
 
      11-20-2011
KJ

The idea of textual PCB design entry is a small paradigm shift and a
lot of people react emotionally so thanks for your comments.

Everybody I know uses VHDL or Verilog for even very simple CPLD
designs. Of course, for large FPGA's and ASIC design HDL is the
preferred entry method for now.

On board design, I also thought that the analog portions of board
design were best done with schematics, till I tried PHDL. Now I find
that the ability to mix lines of comments with lines of design text
actually makes PHDL more expressive than proprietary schematic entry
methods, even for analog circuits.

Also, at least for the kinds of board I do, PCB design is getting
simpler over time. What used to require a board full of ECL logic now
easily runs inside a low cost FPGA. Switching regulators used to be
quite a challenge to capture. These days, I always use an integrate
controller that usually includes the power FET and often includes the
required inductor as well. It only takes a few lines of PHDL (plus
comments) to capture a switching regulator design.

You are right, I don't have any hard data on productivity but I have
been using schematic entry for over twenty years and now I have done
several designs in PHDL. My subjective impression is that PHDL is
faster, more accurate, more readable and less annoying than
proprietary graphical schematic tools. I use the Vim text editor and
we wrote a sytax highlighter control file for Vim that makes PHDL
design entry really pleasant. When working with schematic entry tools
I keep track of how much time I spend on non-productive tool fiddling
and how much on actual design entry. I think it is 90% fiddling and
10% actual work. In PHDL, I feel the ratio is reversed, 10% fiddling
and 90% design entry.

With respect to efficiency, I find that pure text PHDL design entry
actually requres less typing than the schematic editor that I normally
use (Mentor DxDesigner). I find most of the text can be autogenerated
(FPGA) or cut and pasted from the pdf data sheet. I find the
reduction of typing (and fiddling) really reduces my error rate and
lets me focus on the actual design. Again, this is just an objective
observation. Let me know what you think after you have tried PHDL.

Searching for components by refdes is something that is very unwieldy
in most schematic editor tools. Of course, searching for text within
a text file like PHDL source is very natural. The PHDL compiler
controls the mapping between design pathname and refdes in an open CSV
format file that can be searched to quickly locate any refdes within
the design hierarchy. Furthermore, we are extending the funtionality
of the refdes idea to contain some hierarchical information. This
makes it really easy, in the layout tool, to quickly select all the
components in one part of the design. As far as I know, this is a very
simple but valuable improvement over how schematics usually handle
refdes.

With respect to version control, diff'ing the source design is much
better than diff'ing the machine generated netlist output.

I have actually tried almost all of the graphical logic generation
tools to supposedly improve designer productivity, Xilinx DSP System
Generator, Altera DSP Builder, Aldec BDE block diagram editor,
National Instruments Labview FPGA,... For production designs I always
use strait HDL entry for maintainability. How many proprietary tools
do you want to pay maintenance on just to be able to edit your own
design? PHDL is free and open. You could actually archive the PHDL
compiler (jar file) along with your design for infinite
maintainability.

I am getting together with the compiler designers tomorrow. We are
going to talk about new features for version 2 of PHDL. The new
features will probably include

1) Hierarchical design - for modularity. Once we have this, PHDL won't
be linear text but, instead, organized functionally.
2) VHDL output - for design analysis, simulation and graphical
viewing. This is an easy way to get pictures out of your PHDL design.
3) Altium netlist output - Altium is coming on in popularity. People
request Altium netlist format more than any other.
4) Record Type nets - (maybe) We want to do this better and simpler
than VHDL. Ie., we want to be able to combine inputs and outputs in a
single record.
5) Full parser re-write - The guys want to do a little "refactoring"
now that they have written a compiler and are a lot smarter.

Once again, thanks for the comments and ideas. The very fact that you
guys are participating on this usenet group means you are looking for
new ideas. Maybe PHDL is not for you.

Best wishes,

Pedro


 
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Andy
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Posts: n/a
 
      11-23-2011
On Nov 20, 11:15*am, self <(E-Mail Removed)> wrote:
>
> 1) Hierarchical design - for modularity. Once we have this, PHDL won't
> be linear text but, instead, organized functionally.


How will it handle reference designators when you instantiate the same
hierarchical module more than once in a design? Are reference
designators now required to be hierarchical paths?

Most schematic entry tools do not require you to define a reference
designator when you instantiate the component, they will do that
automatically when the extract the netlist (and annotate a cross-
reference for you). And they will allow board layout to resequence
them per physical location once the components are placed on the
board. Unlike the pdf schematic which is searcable, when I'm probing
the board, there is no search feature for it. That's why I infinitely
prefer reference designators sequenced per layout, not per schematic
organization.

Now that schematic drawings are ultimately released as a multi-page
pdf with searchable text, the advantages of a textual netlist over a
schematic are nil, while the disadvantages are considerable. Tools
exist for graphically comparing two schematic versions to easily
identify the changes, even when they are "cosmetic". Keep in mind that
what you may consider "cosmetic" may be critical to the understanding
imparted to the reader. Comments are cosmetic too, but very useful.

Must you entirely re-define a component that is in a different
package? Most systems separate logical parts that get instantiated
from physical packages that are included in the netlist for a variety
of reasons (e.g. multiple package choices per instantiated logical
part, multiple logical parts per physical package, etc.). How does/
will PHDL handle these scenarios?

Cadence had a spreadsheet-type system that was an alternative to
schematic capture for board design. It might have worked pretty well
for backplane design, but was a complete dud for general purpose board
design.

I can easily see that if you use integrated power supply controllers
as the extent of your analog design, then you may not appreciate the
contextual awareness that a schematic diagram provides over a netlist.
Most non-trivial analog circuits are easier to understand when
presented appropriately in a graphical context. Spice may be
universal, but nobody uses it to convey a circuit to another human.
Don't underestimate the value of a well-drawn schematic (not a
computer generated one) for the customer, reviewers, maintainers,
technicians, etc. Even in FPGA design, I often long for the ability to
re-arrange a computer generated diagram of my code for presentation,
documentation, etc.

Productivity is a lot more than simply getting a design out of your
head and into a board. And therein are the shortcomings of text-based
board design.

Andy

 
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gideon.zweijtzer@gmail.com
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Posts: n/a
 
      07-04-2012
On Friday, October 28, 2011 4:28:14 AM UTC+2, self wrote:
> Guys
>
> I want to give you an update on the HDL for PCB work I have been
> doing. Lately I have collaborated with the Configurable Computing Lab
> at Brigham Young University to introduce a new, super simple HDL for
> board design capture. A compiler has been written and tested on a few
> board designs.
>


Hi!

How cool that you're working on this. I had been looking on the web, but I had not found anything yet. At our company we are doing something very similar, and we've designed a syntax that is highly optimized for electronic design entry. We are just starting to build the compiler, so you're probably ahead quite a bit. On the other hand, I see that your language is indeed simple; probably a bit too simple to effectively describe circuits.

I also do understand the almost "angry" or "upset" replies from some guys here. Hardware guys don't like change, usually. And people who THINK in schematics can't grasp the great advantages of text over anything graphical. The same happened when FPGAs came into existence. I wouldn't want to feed themouths of those who have actually drawn schematics with logic gates to do FPGA design.

We see that the advantages of text entry are so great, that we have stoppedusing any graphical tool for FPGA designs years ago, with great success. Ido believe that for electronic designs the same advantages exist.

However, there are some questions that remain to be answered. I'd really beinterested to talk to you about this 'off line'.

With kind regards,
Gideon
 
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fabrizio.tappero@gmail.com
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      07-09-2012
Just to be informative, KiCad is a great open-source software tool to make PCBs
http://www.kicad-pcb.org

on top of that, there is a great on-going effort in making is scriptable:
http://www.kicad-pcb.org/display/~aj...ripting+Branch


Considering this, I am not sure (in this field) so much more can be invented to make the life of PCB developers easier.

my 2c

cheers
Fabrizio

 
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