Synthesizable VHDL

shaiko

Junior Member

Join Date: Sep 2011

Posts: 3

09-14-2011

Hello people,

Can the following VHDL code be synthesized?

"input <= (conv_integer(number) => '1', others => '0');"

notes:
1."input" is defined as an std_logic_vector(15 downto 0) signal.
2."number" is defined an integer signal with a range of 0 to 15 ("number" isn't a constant).

Thread Tools
Show Printable Version Email this Page

Posting Rules
You may not post new threads You may not post replies You may not post attachments You may not edit your posts BB code is On Smilies are On [IMG] code is On HTML code is Off Trackbacks are On Pingbacks are On Refbacks are Off Forum Rules

Similar Threads
Thread	Thread Starter	Forum	Replies	Last Post
synthesizable delay using vhdl	ravi33811	VHDL	0	09-13-2007 04:02 AM
Is floating_pkg (VHDL-2006) synthesizable ?	Ved	VHDL	2	11-07-2006 08:33 AM
Synthesizable VHDL	aravind	VHDL	2	10-30-2006 05:18 PM
question on timing in synthesizable vhdl	Mike Treseler	VHDL	5	09-13-2005 10:07 AM
SOS! newbie question about synthesizable VHDL : synthesis run successfully but post-synthesis failed...	walala	VHDL	4	09-09-2003 08:41 AM