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Would you like the alternative to Zero Ohm?

 
 
valtih1978
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      09-09-2011
Notorious Ben Cohen's Zero Ohm model is recommended wherever you need a
delay in a bi-dir line. But, have you tried it yourself?

It corrupts your signal as much as the delay it is asked to introduce
(see the diagrams
http://valjok.blogspot.com/2011/08/h...-zero-ohm.html)!
I had to simulate a DDR-400 (a transfer every 2.5 ns) with 4.5 ns borad
delay. No chance.

It seems that Ben introduces the Z-state into target signal every driver
transaction. This is done to break feedbacks in bi-dir channel. However,
the lines are normally half-duplex. There is no need to simulate the
reflections or another end driver while current driver is broadcasting.
User introduces the z-state moments himslef when switches between
signle-driver modes. He needs z-gap to prevent driver congestion. He
does this in appropriate time, only once per direction switch. Based on
that, I have created an alternative switch model. It detects the driver
broadcast direction automatically, by watching who breaks the z-state,
and serves as repeater then.

entity Z_SWITCH is
generic (LAG: time := 1 ns);
port (
A, B: inout std_logic := 'Z' -- must be Z-separated or A takes
precedence
);
end entity;

architecture WAIT_FOR_Z of Z_SWITCH is
procedure P(constant NAME: string; signal X: in std_logic; variable
X_TIMEOUT: in time;
signal Y: out std_logic; variable Y_TIMEOUT: inout time) is
begin
if now > X_TIMEOUT and X /= 'Z' then
L1: loop
Y <= transport X after LAG;
Y_TIMEOUT := now + LAG;
if X = 'Z' then
exit L1;
end if;
wait on X;
end loop;
end if;

end procedure;

begin

process
variable A_TO, B_TO: time := - 10 ns; -- signal will propagate
up to this time, do not loop it back.
begin
wait on A, B;
P("A->B", A, A_TO, B, B_TO); -- until A iz not Z
P("B->A", B, B_TO, A, A_TO); -- until B is not Z
end process;

end architecture;

This defeats the joy of simulation the strong-weak interaction during
the congestion. But, at least, the normal signal is not destroyed. No
more corruption instead of delay!


Do you still give links to Ben Cohen?
 
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hdlcohen@gmail.com
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Posts: n/a
 
      09-11-2011
On Sep 9, 7:21*am, valtih1978 <(E-Mail Removed)> wrote:
> Notorious Ben Cohen's Zero Ohm model is recommended wherever you need a
> delay in a bi-dir line. But, have you tried it yourself?
>
> It corrupts your signal as much as the delay it is asked to introduce
> (see the diagramshttp://valjok.blogspot.com/2011/08/half-duplex-better-than-zero-ohm.h...
> I had to simulate a DDR-400 (a transfer every 2.5 ns) with 4.5 ns borad
> delay. No chance.
>
> It seems that Ben introduces the Z-state into target signal every driver
> transaction. This is done to break feedbacks in bi-dir channel. However,
> the lines are normally half-duplex. There is no need to simulate the
> reflections or another end driver while current driver is broadcasting.
> User introduces the z-state moments himslef when switches between
> signle-driver modes. He needs z-gap to prevent driver congestion. He
> does this in appropriate time, only once per direction switch. Based on
> that, I have created an alternative switch model. It detects the driver
> broadcast direction automatically, by watching who breaks the z-state,
> and serves as repeater then.
>
> entity Z_SWITCH is
> * * generic (LAG: time := 1 ns);
> * * port (
> * * * * A, B: inout std_logic := 'Z' -- must be Z-separated or A takes
> precedence
> * * );
> end entity;
>
> architecture WAIT_FOR_Z of Z_SWITCH is
> procedure P(constant NAME: string; signal X: in std_logic; variable
> X_TIMEOUT: in time;
> * * signal Y: out std_logic; variable Y_TIMEOUT: inout time) is
> begin
> * * * * if now > X_TIMEOUT and X /= 'Z' then
> * * * * * * L1: loop
> * * * * * * * * Y <= transport X after LAG;
> * * * * * * * * Y_TIMEOUT := now + LAG;
> * * * * * * * * if X = 'Z' then
> * * * * * * * * * * exit L1;
> * * * * * * * * end if;
> * * * * * * * * wait on X;
> * * * * * * end loop;
> * * * * end if;
>
> end procedure;
>
> begin
>
> * * process
> * * * * variable A_TO, B_TO: time := - 10 ns; -- signal will propagate
> up to this time, do not loop it back.
> * * begin
> * * * * wait on A, B;
> * * * * P("A->B", A, A_TO, B, B_TO); -- until A iz not Z
> * * * * P("B->A", B, B_TO, A, A_TO); -- until B is not Z
> * * end process;
>
> end architecture;
>
> This defeats the joy of simulation the strong-weak interaction during
> the congestion. But, at least, the normal signal is not destroyed. No
> more corruption instead of delay!
>
> Do you still give links to Ben Cohen?


Links to my models is available from
VhdlCohen PublishingListing of directory: /vhdlcohen/vhdl
http://bit.ly/pCu5Xx
I also uploaded it http://systemverilog.us/zohm0_ea.vhd
There is also http://systemverilog.us/switch1.vhd
--------------------------------------------------------------------------
Ben Cohen (831) 345-1759
http://www.systemverilog.us/ [e-mail address removed]
* SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN
878-0-9705394-8-7
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition,
2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example, 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN
0-7923-8115
--------------------------------------------------------------------------
 
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