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Fast Counter

Posts: n/a
> Actually it has everything to do with 'it', but you do not seem to be
understanding 'it'.

Thanks. Next time, I will know that redundancy adds very much because
"it also has to do with it".

> Not true at all...see previous paragraph...and you should probably

research the definition of computer as well.

I know the right definition! Computers are the people who do
computations! FPGAs fall into absolutely different category!

> Not true either. A discrete logic gate implementation or a discrete

transistor implementation would be much slower than an FPGA

Good job. To be more honest, you had to compare the latest integral
nanoscale desktop processor against large mechanical relay logic from
30-ties. The first computers used that technology. This way, you would
have proven much stronger thesis: our flexible SW completely outdoes any
HW implementation!

Following this line of reasoning, we can recall that first uProcessors
were running at 1 mhz. Today FPGAs can emulate them 100 times faster.
Now, people must stop thinking that FPGAs are slower than ASIC
implementation. I just cannot understand why today 4 GHz processor can
run at 400 mhz maximum when implemented in FPGA?

>As does an ASIC design...unless you really think that ASIC designers

design everything down to the transistor level. Gates are an

Transistors are an abstraction. –°opper and electrons are an abstraction.
Everything is and abstraction. We like abstractions because they help
use to understand. Me, Xilinx and Synopsys use gate netilst abstraction
to understand the implementation.

> You can choose to use the words 'implementation' and 'emulation' how

you want. However, since those words already have accepted
definitions that are different than what you have chosen don't
expect to get much acceptance of your usage.

How picture of user gates emulated by FPGA can not correspond to this

> This is the last I have to say on this thread.

Thank you for the warning. It would be very nice. We can be prepared.
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Posts: n/a
The very name, FPGA means "gate array", says that FPGA provides the
programmable gates. They are virtual abstractions, like you like to say,
implemented by hard silicon gates at the bottom level. Don't be scared
to distribute this view.
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Posts: n/a
On Sep 18, 5:37*am, valtih1978 <(E-Mail Removed)> wrote:
> I just cannot understand why today 4 GHz processor can
> run at 400 mhz maximum when implemented in FPGA?

That 4 GHz processor won't run at 4 GHz if it is implemented in ASIC
gates either.

Does that mean that ASICs only emulate circuits too? (rhetorical!)


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Posts: n/a

How 4 GHz ASIC, that is capable running at 4 GHz, cannot run at 4 GHz?
Sounds like a controversy.
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Posts: n/a
On Sep 19, 4:57*am, valtih1978 <(E-Mail Removed)> wrote:
> How 4 GHz ASIC, that is capable running at 4 GHz, cannot run at 4 GHz?
> Sounds like a controversy.

No, just function-specific limitations on clock rate. Depends on what
you are trying to do on the chip. Just because a technology is rated
for a given maximum clock rate, does not mean you can calculate pi to
the millionth decimal place in one clock cycle on it.

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John Kent
Posts: n/a
Get a CPU with 800MHZ FSB and put NOPs on the bus

On 8/09/2011 5:07 AM, Jessica Shaw wrote:
> Hi,
> I need a 700 MHz to 800Mhz synchronous 16 bit counter. The counter
> will also have a Start, Reset and Stop pins.
> Reset will intialize the counter to zero. Start will let the counter
> run on each rising edge of the 700 or 800 Mhz clock. And stop will
> stop the counter and user will be able to read the value.
> I do not know
> 1. What FPGA or CPLD will be able to do this task at the above
> mentioned high frequency?
> 2. Do I need a PLL inside the FPGA or CPLD to produce such kind of
> clock?
> 3. How can I generate this kind of clock?
> Any advice will be appreciated.
> jess

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