«

[Daniela]

Hi!! I recently started working with VHDL, and I´m stuck with my design.. What I try to do is to find the best signal/noise+interference ratio (SNIR) from a set of channels.
My design receives in a group of ports (ch_X_state) the state of the channels (busy ('0') /idle ('1')) and in other group of ports (snir_chX), the SINR assigned to every channel. The output ports are the channel (channel) with the best SNIR and a signal (assign) that enables the next stage of the system.
I assigned the input signals to arrays and tried to find the best SNIR using FOR loops. The design is succesfully compiled and synthesized, but nothing happens during the simulation!! The signal assign is never activated, even though it should be active during some cases...
I appreciate all help and comments. Here is the code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity decision_1 is

port (
-- Input ports for channel state (0: busy, 1: idle)
ch_1_state: in std_logic;
ch_2_state: in std_logic;
ch_3_state: in std_logic;
ch_4_state: in std_logic;
ch_5_state: in std_logic;
ch_6_state: in std_logic;
ch_7_state: in std_logic;
ch_8_state: in std_logic;
ch_9_state: in std_logic;
ch_10_state: in std_logic;
-- Input ports for SNIR value
snir_ch1: in std_logic_vector(13 downto 0);
snir_ch2: in std_logic_vector(13 downto 0);
snir_ch3: in std_logic_vector(13 downto 0);
snir_ch4: in std_logic_vector(13 downto 0);
snir_ch5: in std_logic_vector(13 downto 0);
snir_ch6: in std_logic_vector(13 downto 0);
snir_ch7: in std_logic_vector(13 downto 0);
snir_ch8: in std_logic_vector(13 downto 0);
snir_ch9: in std_logic_vector(13 downto 0);
snir_ch10: in std_logic_vector(13 downto 0);

enable: in std_logic;
clock: in std_logic;
-- Output ports
assign: out std_logic;
channel: out std_logic_vector(3 downto 0)
);
end decision_1;

architecture structure of decision_1 is

type ch_state is array (1 to 10) of std_logic;
type snir_value is array (1 to 10) of std_logic_vector(13 downto 0);
type qa_value is array (1 to 10) of std_logic_vector(13 downto 0);

signal ch: ch_state;
signal snir: snir_value;
signal ch_qa: qa_value;
signal max: std_logic_vector(13 downto 0);
signal ch_now: std_logic;
signal snir_now: std_logic_vector(13 downto 0);
signal ch_qa_now: std_logic_vector(13 downto 0);
signal result: std_logic;
signal ch_result: std_logic_vector(3 downto 0);

begin
-- Input signals are assigned to arrays for loop management

ch(1) <= ch_1_state;
ch(2) <= ch_2_state;
ch(3) <= ch_3_state;
ch(4) <= ch_4_state;
ch(5) <= ch_5_state;
ch(6) <= ch_6_state;
ch(7) <= ch_7_state;
ch( <= ch_8_state;
ch(9) <= ch_9_state;
ch(10) <= ch_10_state;

snir(1) <= snir_ch1;
snir(2) <= snir_ch2;
snir(3) <= snir_ch3;
snir(4) <= snir_ch4;
snir(5) <= snir_ch5;
snir(6) <= snir_ch6;
snir(7) <= snir_ch7;
snir( <= snir_ch8;
snir(9) <= snir_ch9;
snir(10) <= snir_ch10;

process(clock, enable)
variable cont: integer range 0 to 10;
begin
if (clock'event and clock = '1') then
if (enable = '1') then
for num in 1 to 10 loop
ch_now <= ch(num);
if (ch_now = '1') then
snir_now <= snir(num);
if (snir_now > "00010010110000") then
ch_qa(num) <= snir(num);
else
ch_qa(num) <= (others => '0');
end if;
else
ch_qa(num) <= (others => '0');
end if;
end loop;
-- this logic is to find the maximum SNIR
if ((ch_qa(1) > ch_qa(2)) and
(ch_qa(1) > ch_qa(3)) and
(ch_qa(1) > ch_qa(4)) and
(ch_qa(1) > ch_qa(5)) and
(ch_qa(1) > ch_qa(6)) and
(ch_qa(1) > ch_qa(7)) and
(ch_qa(1) > ch_qa() and
(ch_qa(1) > ch_qa(9)) and
(ch_qa(1) > ch_qa(10))) then
max <= ch_qa(1);
elsif
((ch_qa(2) > ch_qa(3)) and
(ch_qa(2) > ch_qa(4)) and
(ch_qa(2) > ch_qa(5)) and
(ch_qa(2) > ch_qa(6)) and
(ch_qa(2) > ch_qa(7)) and
(ch_qa(2) > ch_qa() and
(ch_qa(2) > ch_qa(9)) and
(ch_qa(2) > ch_qa(10)) and
(ch_qa(2) > ch_qa(1))) then
max <= ch_qa(2);
elsif
((ch_qa(3) > ch_qa(4)) and
(ch_qa(3) > ch_qa(5)) and
(ch_qa(3) > ch_qa(6)) and
(ch_qa(3) > ch_qa(7)) and
(ch_qa(3) > ch_qa() and
(ch_qa(3) > ch_qa(9)) and
(ch_qa(3) > ch_qa(10)) and
(ch_qa(3) > ch_qa(1)) and
(ch_qa(3) > ch_qa(2))) then
max <= ch_qa(3);
elsif
((ch_qa(4) > ch_qa(5)) and
(ch_qa(4) > ch_qa(6)) and
(ch_qa(4) > ch_qa(7)) and
(ch_qa(4) > ch_qa() and
(ch_qa(4) > ch_qa(9)) and
(ch_qa(4) > ch_qa(10)) and
(ch_qa(4) > ch_qa(1)) and
(ch_qa(4) > ch_qa(2)) and
(ch_qa(4) > ch_qa(3))) then
max <= ch_qa(4);
elsif
((ch_qa(5) > ch_qa(6)) and
(ch_qa(5) > ch_qa(7)) and
(ch_qa(5) > ch_qa() and
(ch_qa(5) > ch_qa(9)) and
(ch_qa(5) > ch_qa(10)) and
(ch_qa(5) > ch_qa(1)) and
(ch_qa(5) > ch_qa(2)) and
(ch_qa(5) > ch_qa(3)) and
(ch_qa(5) > ch_qa(4))) then
max <= ch_qa(5);
elsif
((ch_qa(6) > ch_qa(7)) and
(ch_qa(6) > ch_qa() and
(ch_qa(6) > ch_qa(9)) and
(ch_qa(6) > ch_qa(10)) and
(ch_qa(6) > ch_qa(1)) and
(ch_qa(6) > ch_qa(2)) and
(ch_qa(6) > ch_qa(3)) and
(ch_qa(6) > ch_qa(4)) and
(ch_qa(6) > ch_qa(5))) then
max <= ch_qa(6);
elsif
((ch_qa(7) > ch_qa() and
(ch_qa(7) > ch_qa(9)) and
(ch_qa(7) > ch_qa(10)) and
(ch_qa(7) > ch_qa(1)) and
(ch_qa(7) > ch_qa(2)) and
(ch_qa(7) > ch_qa(3)) and
(ch_qa(7) > ch_qa(4)) and
(ch_qa(7) > ch_qa(5)) and
(ch_qa(7) > ch_qa(6))) then
max <= ch_qa(7);
elsif
((ch_qa( > ch_qa(9)) and
(ch_qa( > ch_qa(10)) and
(ch_qa( > ch_qa(1)) and
(ch_qa( > ch_qa(2)) and
(ch_qa( > ch_qa(3)) and
(ch_qa( > ch_qa(4)) and
(ch_qa( > ch_qa(5)) and
(ch_qa( > ch_qa(6)) and
(ch_qa( > ch_qa(7))) then
max <= ch_qa(;
elsif
((ch_qa(9) > ch_qa(10)) and
(ch_qa(9) > ch_qa(1)) and
(ch_qa(9) > ch_qa(2)) and
(ch_qa(9) > ch_qa(3)) and
(ch_qa(9) > ch_qa(4)) and
(ch_qa(9) > ch_qa(5)) and
(ch_qa(9) > ch_qa(6)) and
(ch_qa(9) > ch_qa(7)) and
(ch_qa(9) > ch_qa()) then
max <= ch_qa(9);
else
max <= ch_qa(10);
end if;
-- max signal contains the maximum SNIR
if (max = "0000000000000") then
assign <= '0';
channel <= (others => '0');
else
cont := 0;
for con in 1 to 10 loop
cont := cont + 1;
ch_qa_now <= ch_qa(con);
if (ch_qa_now = max) then
assign <= '1';
channel <= conv_std_logic_vector(cont,4);
exit;
end if;
end loop;
end if;
end if;
end if;
end process;


end structure;

[tesscar]

Hi Daniela,

I believe the problem is in the use of variables in your design (i.e., variable cont: integer range 0 to 10

and the statement -

cont := 0;
for con in 1 to 10 loop
cont := cont + 1;

There are constructs in VHDL that are "behavioral" and can be simulated, but are not "synthesizable" into actual hardware. You may have to find another way of doing the above statement with code that is synthesizable. In general, do a google search on "behavioral verses synthesizable VHDL" and you might find some general information.

Good Luck!

Tesscar

[Daniela]

Hi Tesscar,

I have instantiated a counter as a component and changed the design using a state machine, now the project seems to work fine...

Thanks for your advices, they were really helpful

Daniela