«

Martin Thompson <> writes:

> Hi all,
>
> I'm asking for a bit of input from the community...
>
> As the title says, would you find it of use to allow Unicode identifiers
> and comments in a future VHDL revision?
>
> Would this be:
> c) Something you'd find useful sometimes

I liked an example snippet in Python I saw some time ago. There's
another one at
http://programmers.stackexchange.com...variable-names

for example.

After all, if your angle is phi, then why bother writing it out when
you can just use 'φ' instead?

> After all, if your angle is phi, then why bother writing it out when
> you can just use 'φ' instead?

I like that example. I prefer to write math equations using symbols too, rather than typing in 'English'. Sometimes, greek is better than english whenit comes to math/physics... IMO.

I may not be answering the question, but I will vote:
f) something that the VHDL standard shouldn't be concerned about.

Let the tool vendors concern themselves on this when they have enough customer demand. I believe I won't face much problems when I'm using two different vendor tools (say for synthesis and simulation) who both claim to be Unicode-compliant.

On Thursday, July 28, 2011 12:13:48 PM UTC-7, Martin Thompson wrote:
> Hi all,
>
> I'm asking for a bit of input from the community...
>
> As the title says, would you find it of use to allow Unicode identifiers
> and comments in a future VHDL revision?
>
> Would this be:
> a) Something VHDL should not allow
> b) Something that doesn't bother you either way
> c) Something you'd find useful sometimes
> d) Something you'd make use of all the time
> e) Something that you'd switch away from SystemVerilog just to get at
> (maybe I'm asking the wrong crowd for that
>
> Thanks,
> Martin
>
> --
> http://parallelpoints.com/

> a) Something VHDL should not allow

Comments would be fine. I am more worried about the entire toolchain: netlist representation, p&r tools, graphical visualization.


- Daniel