«

Mr. Google did not find this article/book (I don't know what it is).
Mr. Amazon did not find this article/book (same as before...).

It is mentioned in the vmkr documentation by Bell-Northern Research VHDL
Group
(http://www.pldworld.com/_hdl/1/tech-...oc/vmkr.doc.ps)
but no other references found.

Does anyone know where I can find this article/book?

As a parting note, does anyone have any suggestion/recommendation on the
usage of vmkr?

Al

--
A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

On Jul 19, 3:36*am, Alessandro Basili <alessandro.bas...@cern.ch>
wrote:
> Mr. Google did not find this article/book (I don't know what it is).
> Mr. Amazon did not find this article/book (same as before...).
>
> It is mentioned in the vmkr documentation by Bell-Northern Research VHDL
> Group
> (http://www.pldworld.com/_hdl/1/tech-...hamburg.de/vhd...)
> but no other references found.
>
> Does anyone know where I can find this article/book?
>
> As a parting note, does anyone have any suggestion/recommendation on the
> usage of vmkr?

Google provides some links if you just search for "makefiles
bergeron":
- www.vhdl.org/misc/ModelingGuidelines.paper.ps
- pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf

Regards,
Daniel

On 7/20/2011 7:14 PM, Daniel Leu wrote:
> Google provides some links if you just search for "makefiles
> bergeron":
> - www.vhdl.org/misc/ModelingGuidelines.paper.ps

This (IMHO very interesting) article is "Guidelines for Writing VHDL
Models in a Team Environment".

> - pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf
>

This is "Managing VHDL Models with Makefiles".

Thanks for pointing them out, I'm trying to subscribe to "Verification
Guild" but I still have some problems.

On 7/20/2011 1:31 AM, Alan Fitch wrote:
> Try posting your message on the Verification Guild
> http://verificationguild.com (I think, from memory). Janick started the
> website, and often posts there,
>

In case somebody maybe interested, the article in the subject is indeed
this one:

"Managing VHDL Models with Makefiles" by Janick Bergeron
(http://pldworld.pe.kr/_hdl/1/RESOURC...rary/mb004.pdf)

On 24 Jul., 00:27, Alessandro Basili <alessandro.bas...@cern.ch>
wrote:
> On 7/20/2011 1:31 AM, Alan Fitch wrote:
>
> > Try posting your message on the Verification Guild
> >http://verificationguild.com(I think, from memory). Janick started the
> > website, and often posts there,
>
> In case somebody maybe interested, the article in the subject is indeed
> this one:
>
> "Managing VHDL Models with Makefiles" by Janick Bergeron
> (http://pldworld.pe.kr/_hdl/1/RESOURC...rary/mb004.pdf)




Where can the tools described be downloaded ?

Cheers, hssig

On 7/25/2011 2:57 PM, hssig wrote:
In case somebody maybe interested, the article in the subject is indeed
>> this one:
>>
>> "Managing VHDL Models with Makefiles" by Janick Bergeron
>> (http://pldworld.pe.kr/_hdl/1/RESOURC...rary/mb004.pdf)
>
>
>
>
> Where can the tools described be downloaded ?
>

http://sourceforge.net/projects/vmk/

> Cheers, hssig
>

Is there a possibility to use that tool under Windows (7) ? How do I
have to install it?

Cheers,
hssig

On 7/27/2011 2:36 PM, hssig wrote:
> Is there a possibility to use that tool under Windows (7) ? How do I
> have to install it?

I think it is possible, if you have cygwin installed:

http://www.cygwin.com/

you should be able to install with a simple "make" command from the top
level directory.
I have to say I have not tried it yet. Just looking into it these days.

>
> Cheers,
> hssig
>

On 27/07/2011 13:36, hssig wrote:
> Is there a possibility to use that tool under Windows (7) ? How do I
> have to install it?
>
> Cheers,
> hssig
>

As suggested earlier why don't you simply use vmake from Modelsim?

Vmake can be used without a valid license (just extract after running
the installer). Use vcom (also no valid license required) to compile
your design followed by running vmake.

You can now use any make program under windows (I use nmake from Visual
C++) to process it.

Vmake can also handle Verilog files but unfortunately not SystemC.

Good luck,

Hans
www.ht-lab.com

HT-Lab wrote:

> On 27/07/2011 13:36, hssig wrote:
>> Is there a possibility to use that tool under Windows (7) ? How do I
>> have to install it?
>>
>> Cheers,
>> hssig
>>
>
> As suggested earlier why don't you simply use vmake from Modelsim?

The major difference of course between vmake and a program like vmk is that
vmake creates a makefile from already compiled libraries and that vmk
creates a makefile directly from the VHDL sources.

So for the initial compilation vmk must be used. Or manual compilation, and
optional use of the vcom option "-just eapbc" and wildcards for the VHDL
files. But that does not always work, for example if packages uses other
packages from the same library.

For keeping libraries up to date vmake might be more convenient to use.

I use both vmake and vmk.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.