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1to8 Demux code, can you look plz

 
 
majmoat_ensan
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      07-17-2011
Hi all,

I am tried to write VHDL code for 1 to 8 Demux and that's what i
finish with it

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;


ENTITY Dmux1to8 IS
PORT ( X : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(0 TO 2);
En : IN STD_LOGIC;
W : OUT STD_LOGIC_VECTOR(0 TO 7));
END Dmux1to2;

ARCHITECTURE Structure OF Dmux1to8 IS
SIGNAL m : STD_LOGIC_VECTOR(0 TO 5);

BEGIN
G1: FOR i IN 0 TO 1 GENERATE
Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X);
G2: FOR i IN 2 TO 5 GENERATE
Dec_left: Demux1to2 PORT MAP ( m(i), S(1));
END GENERATE ;
END GENERATE ;
Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO
7) );

END Structure;


can any one told me if is it right or not?
if there are any mistakes can you help me to correct it ?
 
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Nicolas Matringe
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Posts: n/a
 
      07-17-2011
Le 17/07/2011 03:02, majmoat_ensan a écrit :
> Hi all,


Hi

> I am tried to write VHDL code for 1 to 8 Demux and that's what i
> finish with it
>
> LIBRARY IEEE;
> USE IEEE.STD_LOGIC_1164.ALL;
> use ieee.std_logic_unsigned.all;


Do NOT use non-standard libraries like std_logic_arith, std_logic_signed
or std_logic_unsigned. Use numeric_std instead.


> ENTITY Dmux1to8 IS
> PORT ( X : IN STD_LOGIC;
> S : IN STD_LOGIC_VECTOR(0 TO 2);
> En : IN STD_LOGIC;
> W : OUT STD_LOGIC_VECTOR(0 TO 7));
> END Dmux1to2;


Although it doesn't change anything in terms of behaviour, it is common
practice to declare vectors with a descending range (e.g. 7 downto 0)
because the higher index bit is then the leftmost bit (which helps a lot
when you use arithmetic vectors)


> ARCHITECTURE Structure OF Dmux1to8 IS
> SIGNAL m : STD_LOGIC_VECTOR(0 TO 5);
>
> BEGIN
> G1: FOR i IN 0 TO 1 GENERATE
> Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X);
> G2: FOR i IN 2 TO 5 GENERATE
> Dec_left: Demux1to2 PORT MAP ( m(i), S(1));
> END GENERATE ;
> END GENERATE ;
> Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO
> 7) );


There are spaces in your (intended) component name. You can't do this.
Besides, it is also common practice to use named association for port
maps because it is much less error prone (but is adds a lot of typing
unless you use an Editor with MACroS)

> END Structure;


It is absolutely impossible to say if this is good or not because you
don't give the code for components demux1to2 and demux1to8. I find it
strange that you map the same demux1to2 component with 3 ports in your
first generate loop and only 2 ports in the second one.

Nicolas
 
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jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      07-17-2011
Alternative solution for a 74138 - E1 or E2 can be used for datainput.

Code:
process (E1,E2,E3,A2,A1,A0)
    variable Select: stdlogic_vector( 2 downto 0);

begin
    Select := A2 & A1 & A0;
    W      <= "11111111";         -- Default output
    if (E1='0' and E2='0' and E3='1') then
         W( conv_integer( Select)) <= '0';
   end if;
end process;
 

Last edited by jeppe; 07-17-2011 at 04:14 PM..
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majmoat_ensan
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Posts: n/a
 
      07-20-2011
On Jul 18, 7:24*pm, Rob Gaddi <(E-Mail Removed)> wrote:
> On 7/17/2011 12:48 AM, Nicolas Matringe wrote:
>
>
>
>
>
>
>
>
>
> > Le 17/07/2011 03:02, majmoat_ensan a écrit :
> >> Hi all,

>
> > Hi

>
> >> I am tried to write VHDL code for 1 to 8 Demux and that's what i
> >> finish with it

>
> >> LIBRARY IEEE;
> >> USE IEEE.STD_LOGIC_1164.ALL;
> >> use ieee.std_logic_unsigned.all;

>
> > Do NOT use non-standard libraries like std_logic_arith, std_logic_signed
> > or std_logic_unsigned. Use numeric_std instead.

>
> >> ENTITY Dmux1to8 IS
> >> PORT ( X : IN STD_LOGIC;
> >> S : IN STD_LOGIC_VECTOR(0 TO 2);
> >> En : IN STD_LOGIC;
> >> W : OUT STD_LOGIC_VECTOR(0 TO 7));
> >> END Dmux1to2;

>
> > Although it doesn't change anything in terms of behaviour, it is common
> > practice to declare vectors with a descending range (e.g. 7 downto 0)
> > because the higher index bit is then the leftmost bit (which helps a lot
> > when you use arithmetic vectors)

>
> >> ARCHITECTURE Structure OF Dmux1to8 IS
> >> SIGNAL m : STD_LOGIC_VECTOR(0 TO 5);

>
> >> BEGIN
> >> G1: FOR i IN 0 TO 1 GENERATE
> >> Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X);
> >> G2: FOR i IN 2 TO 5 GENERATE
> >> Dec_left: Demux1to2 PORT MAP ( m(i), S(1));
> >> END GENERATE ;
> >> END GENERATE ;
> >> Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO
> >> 7) );

>
> > There are spaces in your (intended) component name. You can't do this.
> > Besides, it is also common practice to use named association for port
> > maps because it is much less error prone (but is adds a lot of typing
> > unless you use an Editor with MACroS)

>
> >> END Structure;

>
> > It is absolutely impossible to say if this is good or not because you
> > don't give the code for components demux1to2 and demux1to8. I find it
> > strange that you map the same demux1to2 component with 3 ports in your
> > first generate loop and only 2 ports in the second one.

>
> > Nicolas

>
> Also, you reused 'i' as your loop variable in the inner loop.
>
> --
> Rob Gaddi, Highland Technology
> Email address is currently out of order



ummm if i tried to wrote it in this way is it right or not?


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;


ENTITY Dmux1to8 IS
PORT ( X : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(0 TO 2);
W : OUT STD_LOGIC_VECTOR(0 TO 7));
END Dmux1to8;

ARCHITECTURE Structure OF Dmux1to8 IS
SIGNAL m : STD_LOGIC_VECTOR(0 TO 5);

BEGIN
Dmux1: Dmux1to8 PORT MAP
( X, s(0), m(0), m(1) ) ;
Dmux2: Dmux1to8 PORT MAP
( m(0), s(1), m(2), m(3) ) ;
Dmux3: Dmux1to8 PORT MAP
( m(1), s(1), m(4), m(5) ) ;
Dmux4: Dmux1to8 PORT MAP
( m(2), s(2), w(0), w(1) ) ;
Dmux5: Dmux1to8 PORT MAP
( m(3), s(2), w(2), w(3) ) ;
Dmux6: Dmux1to8 PORT MAP
( m(4), s(2), w(4), w(5) ) ;
Dmux7: Dmux1to8 PORT MAP
( m(5), s(2), w(6), w(7) ) ;
END Structure ;
 
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KJ
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Posts: n/a
 
      07-20-2011
On Jul 20, 12:35*pm, Rob Gaddi <(E-Mail Removed)> wrote:
>
> What on earth are you actually trying to accomplish


Homework perhaps.
 
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KJ
Guest
Posts: n/a
 
      07-21-2011
On Jul 20, 10:48*am, majmoat_ensan <(E-Mail Removed)>
wrote:

>
> ummm if i tried to wrote it in this way is it right or not?
>


Not.

Not even close (to be more precise)

Consider downloading either a free version of Modelsim or GHDL and
start compiling and simulating your code. The tool will give you must
quicker and more detailed responses to your questions...it will also
let you simulate your design to see if it works as you intend.
Learning by doing is a very effective method.

Kevin Jennings
 
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eliascm eliascm is offline
Member
Join Date: Jan 2009
Posts: 42
 
      07-28-2011
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------------------------------------------------------------------------
ENTITY demux IS

PORT ( sig_in : IN std_logic;
sel : IN std_logic_vector(2 downto 0);
sig_out : OUT std_logic_vector(7 downto 0)
);
END demux;

ARCHITECTURE structure OF demux IS

BEGIN
p_demux: process(sel, sig_in)
begin
for i in 0 to 7 loop
if unsigned(sel) = i then
sig_out(i) <= sig_in;
else
sig_out(i) <= '0';
end if;
end loop;
end process;
END;
 
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