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wait for argument a variable?

 
 
Shannon
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      07-06-2011
Simple question: Can the argument in a "wait for (time)" be a
variable? (in a test bench of course. not worried about synthesis)

i.e.
some_integer := 7
....
holdtime := 10 * some_integer * 1 us;
wait for holdtime;
 
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jeppe jeppe is offline
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Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      07-06-2011
Not sure but try something like this:

holdtime := 10 us * some_integer us;
 
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rpaley000@gmail.com rpaley000@gmail.com is offline
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Join Date: Jul 2011
Posts: 3
 
      07-06-2011
Quote:
Originally Posted by Shannon View Post
Simple question: Can the argument in a "wait for (time)" be a
variable? (in a test bench of course. not worried about synthesis)

i.e.
some_integer := 7
....
holdtime := 10 * some_integer * 1 us;
wait for holdtime;
Yes. The above code will work and will wait for 70 us. See Dr. Ashenden's book (3rd edition) page 59.
 
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KJ
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      07-06-2011
On Jul 6, 4:16*pm, Shannon <(E-Mail Removed)> wrote:
> Simple question: *Can the argument in a "wait for (time)" be a
> variable? *(in a test bench of course. *not worried about synthesis)
>
> i.e.
> some_integer := 7
> ...
> holdtime := 10 * some_integer * 1 us;
> wait for holdtime;


Yes.

KJ

P.S. Wouldn't it be easier to just try this on a simulator rather
than posting to a newsgroup?
 
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Shannon
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      07-07-2011
On Jul 6, 4:08*pm, KJ <(E-Mail Removed)> wrote:
> On Jul 6, 4:16*pm, Shannon <(E-Mail Removed)> wrote:
>
> > Simple question: *Can the argument in a "wait for (time)" be a
> > variable? *(in a test bench of course. *not worried about synthesis)

>
> > i.e.
> > some_integer := 7
> > ...
> > holdtime := 10 * some_integer * 1 us;
> > wait for holdtime;

>
> Yes.
>
> KJ
>
> P.S. *Wouldn't it be easier to just try this on a simulator rather
> than posting to a newsgroup?


My professors always told me to ask questions in class. If I have a
question likely others do too. Thank you for educating more than just
me today.
 
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Alessandro Basili
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      07-07-2011
On 7/7/2011 4:20 AM, Shannon wrote:
> My professors always told me to ask questions in class. If I have a
> question likely others do too. Thank you for educating more than just
> me today.


Your professors are definitely right in telling you so and I am also
very well convinced that none of your professors encouraged you to post
a question on a newsgroup if the answer is readily available somewhere
else or with some minor effort.

In this context I strongly suggest you a couple of readings that will
help you out building relationships in the community:

from the comp.lang.vhdl FAQ:

- http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#0.3

from an interesting link that you can also find in the FAQ but that I
would like to underline as well:

- http://www.catb.org/~esr/faqs/smart-...ns.html#before

For what concerns your question in particular, quoting the "IEEE
Standard VHDL Language Reference Manual" (IEEE Std 1076, 2000 Edition):
> The wait statement causes the suspension of a process statement or a procedure.
> wait_statement ::=
> [ label : ] wait [ sensitivity_clause ] [ condition_clause ] [ timeout_clause ] ;
> sensitivity_clause ::= on sensitivity_list
> sensitivity_list ::= signal_name { , signal_name }
> condition_clause ::= until condition
> condition ::= boolean_expression
> timeout_clause ::= for time_expression


Since your variable/constant is of type TIME, your situation does follow
the standard.

Al

 
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Shannon
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      07-07-2011
wow. seriously? I'm being scolded for asking a simple question.
REALLY?? I mean sorry to put you out. Sorry to massively affect the
traffic in this NG. If it's beneath you to help then DON'T REPLY! Is
this the way you really want to moderate this group? Sheesh. I
apologize if my question was not up to your standards.

P.S. seriously?


On Jul 6, 8:06*pm, Alessandro Basili <(E-Mail Removed)>
wrote:
> On 7/7/2011 4:20 AM, Shannon wrote:
>
> > My professors always told me to ask questions in class. *If I have a
> > question likely others do too. *Thank you for educating more than just
> > me today.

>
> Your professors are definitely right in telling you so and I am also
> very well convinced that none of your professors encouraged you to post
> a question on a newsgroup if the answer is readily available somewhere
> else or with some minor effort.
>
> In this context I strongly suggest you a couple of readings that will
> help you out building relationships in the community:
>
> from the comp.lang.vhdl FAQ:
>
> *-http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#0.3
>
> from an interesting link that you can also find in the FAQ but that I
> would like to underline as well:
>
> *-http://www.catb.org/~esr/faqs/smart-questions.html#before
>
> For what concerns your question in particular, quoting the "IEEE
> Standard VHDL Language Reference Manual" (IEEE Std 1076, 2000 Edition):
>
> > The wait statement causes the suspension of a process statement or a procedure.
> > wait_statement ::=
> > [ label : ] wait [ sensitivity_clause ] [ condition_clause ] [ timeout_clause ] ;
> > sensitivity_clause ::= on sensitivity_list
> > sensitivity_list ::= signal_name { , signal_name }
> > condition_clause ::= until condition
> > condition ::= boolean_expression
> > timeout_clause ::= for time_expression

>
> Since your variable/constant is of type TIME, your situation does follow
> the standard.
>
> Al


 
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Jonathan Bromley
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      07-09-2011
On Thu, 07 Jul 2011 05:06:17 +0200, Alessandro Basili wrote:

>from an interesting link that you can also find in the
> FAQ but that I would like to underline as well:
>
> - http://www.catb.org/~esr/faqs/smart-...ns.html#before


Whoa. First off, what's "not smart" about the OP's
question? It shows inquiry, interest, and a reasonable
grasp of the basics. Looks fine to me. How many VHDL
users do _you_ know who can tell you the _full_ story
about the wait statement? It's complicated and subtle.

Second, let's not get too hung up about Eric Raymond's
priggish and defensive protection of his chosen tribe
of hackers. As usual with his stuff, you'll find much
wisdom in that article - but also much that irritates
and makes little sense outside the self-satisfied
community of hackers. Take with a pinch of salt.

Sure, the OP could have found the answer for himself.
But KJ's suggestion that he try it in a simulator is
disingenuous: tools have bugs, and sometimes support
non-LRM-conforming constructs because some big customer
demanded it, so that's not a safe way to decide what's
OK and what's not. And the VHDL LRM is a very densely
written and highly technical document; it's usually
easier to ask an expert than to ask the LRM, especially
if you're not an experienced LRM wonk.

To Shannon: yes, wait-for can be given an arbitrary
expression provided it yields a result of type "time".
The expression is computed at the moment execution
hits the wait statement, and its value determines
the wait behaviour.
--
Jonathan Bromley
 
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KJ
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      07-10-2011
On Jul 9, 2:36*pm, Jonathan Bromley <(E-Mail Removed)>
wrote:
>
> Sure, the OP could have found the answer for himself. *
> But KJ's suggestion that he try it in a simulator is
> disingenuous:


Perhaps you should re-read my post. I answered the OP's question
straight off, clearly, concisely and politely.

As a postscript, I simply suggested that it would likely be easier to
simply try the idea out rather than posting to a newsgroup and waiting
for an answer (and did not write it in a way that suggested that the
question was somehow beneath the standards of the group).

As I did in this case, there are many times in the past when I've
suggested that people try it out for themselves. That is sound
advice. Trying and doing for yourself in almost all cases makes for a
better learning experience than simply reading the words of others.
Not only that, but sometimes you find that people post rubbish...but
the way that you find out that it is rubbish is by actually trying it
out for yourself. You stating that I was being disingenuous when I
wasn't seems to show that you got torqued by Basili's response and
decided to take it out on both him and me.

You likely know the saying about 'Give a man a fish...'. I gave the OP
the fish as well as a lesson in fishing.

> tools have bugs, and sometimes support
> non-LRM-conforming constructs because some big customer
> demanded it, so that's not a safe way to decide what's
> OK and what's not.


You're off on a tangent here...but OK. But let me also point out that
in the situations you just described the *only* way to demonstrate the
bug or non-conformance is to *use* the tool.

> And the VHDL LRM is a very densely
> written and highly technical document; it's usually
> easier to ask an expert than to ask the LRM, especially
> if you're not an experienced LRM wonk.
>

I agree, but will add
- Many times an 'expert' comes in the form of software that can be
queried rather than the response from a human.
- The human can also be in error as well whether or not they are an
'expert' or not.

Learning can come about in many ways, don't discount any
method...unless it has really been shown to be a poor learning method,
or a method that just simply doesn't work for you.

Kevin Jennings
 
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Jonathan Bromley
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      07-10-2011
On Sat, 9 Jul 2011 18:32:42 -0700 (PDT), KJ wrote:

>As a postscript, I simply suggested that it would likely be easier to
>simply try the idea out rather than posting to a newsgroup and waiting
>for an answer (and did not write it in a way that suggested that the
>question was somehow beneath the standards of the group).


Accepted.

> You stating that I was being disingenuous when I
>wasn't seems to show that you got torqued by Basili's response and
>decided to take it out on both him and me.


Could be, although I still think it's worth pointing out the
possible weakness in "trying it out" as a way of checking whether
something is legal in the language. I would never dispute that
experiment is a valuable learning tool, though.

>- Many times an 'expert' comes in the form of software that can be
>queried rather than the response from a human.
>- The human can also be in error as well whether or not they are an
>'expert' or not.


All entirely true. We're in a field where Stuff Is Complicated,
and any source of information - experts, commonsense, software,
even the LRM - can be flawed by human error. Oftentimes the answer
is simple, unambiguous and pretty much universally agreed. But
you need to be on your guard for those few places where something
goes wrong.

For context, and as an excuse: I'm struggling right now (along
with a lot of colleagues) on migrating a large codebase from
one tool to another, and finding that their LRM conformance
is <cough> imperfect. So I'm a tad sensitive about
such things. Should mention, though, that my woes are with
SystemVerilog. VHDL is much better specified and less messy.
--
Jonathan Bromley
 
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