hi, consider the following mux code

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity examp1_pg165 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sel : in STD_LOGIC;
y : out STD_LOGIC);
end examp1_pg165;
architecture Behavioral of examp1_pg165 is
begin
y<= a + b when sel='1' else
a+c ;
end Behavioral;

this gives an error in xilinX ISE as

Code:

+ can not have such operands in this context.

1)So, even after including numeric library, I cannot use '+' with std_logic?

2) so, do i need to convert to signed/unsigned and then add?

3) what is the safest way to use numeric libraries?

Code:

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

or

Code:

use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

some authors say, unsigned library is not needed, others say, signed is not needed.

while some say, do not use std_logic_arith with signed/unsigned.

between numeric_std and std_logic_arith, one can make a choice based upon the operators defined. I believe, if more type conversions are needed, std_logic_arith would be better as it has more operator overloading, but it no Boolean operators?

4) The else clause covers other std_logic values. for synthesis point of view, suppose sel takes 'z', then too, y<-a+c. In real world application, would we do this, or write disconnect the mux by using something like

Code:

y<= a + b when sel='1' else
a+c when sel ='0' else
'z';

Thanks

sid