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how to enter this bus notation

 
 
pfrogge pfrogge is offline
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Join Date: Jun 2011
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      06-13-2011
Hi, trying to transition from verilog RTL design, in that language I could create a bus that was a mixture of constants and variables as follows, how can I do this in VHDL?

{1,0,CS0,1,0,0,CLK,1,0}

thanks in advance.
 
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flymolo flymolo is offline
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      06-20-2011
You can do it in many ways. I guess the most straightforward is:
Code:
'1' & '0' & CS0 & '1' & '0' & '0' & CLK & '1' & '0'
you can group constants:
Code:
b"10" & CS0 & b"100" & CLK & b"10"
 
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pfrogge pfrogge is offline
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      06-20-2011
much appreciated,
thanks
 
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