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ERROR:HDLParsers:164 - "D:/Deepak jena/full_adder/fa.vhd" Line 51. parse error, unexp

dkjena1 dkjena1 is offline
Junior Member
Join Date: Jun 2011
Posts: 1
I am using XILINX ISE 8.1i software and writing code for full adder in structural model. This is my code......

library IEEE;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fa is
Port ( a,b,cin : in STD_LOGIC;
s,co : out STD_LOGIC);
end fa;

architecture Behavioral of fa is
component andgate
port(a1,b1:in std_logic;c1ut std_logic);
end component;
component xorgate
port(a2,b2:in std_logic;c2ut std_logic);
end component;
component orgate
port(a3,b3:in std_logic;c3ut std_logic);
end component;
signal x1,x2,x3:std_logic;
xo1: xorgate portmap(a,b,x1);
xo2: xorgate portmap(cin,x1,s);
a1: andgate portmap(a,b,x3);
a2: andgate portmap(cin,x1,x2);
o1: orgate portmap(x2,x3,co);
end Behavioral;

In this program Syntax check fails and show the following error. can any body help me to solve the problem?

ERROR:HDLParsers:164 - "D:/Deepak jena/full_adder/fa.vhd" Line 51. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACK

Process "Check Syntax" failed
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joris joris is offline
Senior Member
Join Date: Jan 2009
Posts: 152
A space is required between 'port' and 'map'
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