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VHDL 2008 syntax error

 
 
logic_guy
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      05-21-2011
I have been learning about VHDL 2008 and wanted to try a simple example
of the 2008 enhancements. I created the following test file:
entity generic_mux2 is
generic (type data_type);
port (sel : in bit; a, b : in data_type;
z : out data_type );
end entity generic_mux2;

architecture rtl of generic_mux2 is
begin
z <= a when sel = '0' else b;
end architecture rtl;


I installed ModelSim SE 10.0a. It claims to support a significant
subset of the 2008 enhancements. When I try to compile the above file
it get:
vcom -2008 generic_mux2.vhdl
# Model Technology ModelSim SE vcom 10.0a Compiler 2011.02 Feb 20 2011
# -- Loading package STANDARD
# -- Compiling entity generic_mux2
# ** Error: generic_mux2.vhdl(2): near "type": expecting IDENTIFIER
# C:/modeltech_10.0a/win32/vcom failed.

Does ModelSim SE 10.0 not support generic types? Hard to imagine...
This is the first thing mentioned in Peter Ashenden's "VHDL-2008: Just
the New Stuff". (and I copied the above example right out of the book)

Charles Bailey


 
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Mike Treseler
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      05-21-2011
On 5/20/2011 10:01 PM, logic_guy wrote:
> I have been learning about VHDL 2008 and wanted to try a simple example
> of the 2008 enhancements. I created the following test file:
> entity generic_mux2 is
> generic (type data_type);
> port (sel : in bit; a, b : in data_type;
> z : out data_type );
> end entity generic_mux2;
>
> architecture rtl of generic_mux2 is
> begin
> z<= a when sel = '0' else b;
> end architecture rtl;

....
> # ** Error: generic_mux2.vhdl(2): near "type": expecting IDENTIFIER
> # C:/modeltech_10.0a/win32/vcom failed.

)

-- Did you have
library ieee;
use ieee.std_logic_1164.all;
-- at the top?

Would a generic entity need an instance and generic map?

incr_inst : entity work.generic_mux2
generic map ( data_type => std_ulogic)
port map ( ... );

Good luck.

-- Mike Treseler
 
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logic_guy
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      05-21-2011

"Alan Fitch" <(E-Mail Removed)> wrote in message >
> The VHDL 2008 support is documented under Help > Technotes > vhdl2008


Both the vhdl2008 and vhdl2008migration technotes are completely mum
about the topic of generic types. They don't say they support it and
they don't say it's not supported. Apparently, the answer is "no".
(The business of generic types does appear to be a fairly big leap for
the language.)

Charles Bailey


 
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logic_guy
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      05-22-2011

"Mike Treseler" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
>
> -- Did you have
> library ieee;
> use ieee.std_logic_1164.all;
> -- at the top?
>
> Would a generic entity need an instance and generic map?
>
> incr_inst : entity work.generic_mux2
> generic map ( data_type => std_ulogic)
> port map ( ... );
>
> Good luck.
>
> -- Mike Treseler


Adding
library ieee;
use ieee.std_logic_1164.all;
to the top doesn't help. Same error message.

Charles Bailey


 
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hssig
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      05-24-2011
Hi,

I have tried your example with ModelsimPE 10.0b and I got the same
error message.

Cheers,
hssig
 
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