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Having trouble on initialization of array signal

 
 
Tha Tha is offline
Junior Member
Join Date: Apr 2011
Posts: 3
 
      05-09-2011
I am writing a register file..
and I want to assign some initial value to the array
my array have 128 entires and each entire is 128 bit long
however, no matter what format I tried to use..
it kept giving me "???" in my output.
For example, i want to assign x"00000000000001480000000000000000"
but when i simulate..it gave me x"0000000000000???0000000000000000"

Can anyone please help me? thank you so much~
the following are my codes:
Code:
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;  
use ieee.std_logic_arith.all;			   
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_TEXTIO.all;
--use work.constant_lib.all;

entity reg_file is
	port (
	clock : in std_logic;
	rst : in std_logic;
	RFwe1 : in std_logic;
	RFwe2 : in std_logic;
	RFwa1	: 	in std_logic_vector(6 downto 0);-- register address that need to write  
	RFwa2	: 	in std_logic_vector(6 downto 0);-- register address that need to write 
	RFw1	: 	in std_logic_vector(127 downto 0);-- data into register
	RFw2	: 	in std_logic_vector(127 downto 0);-- data into register
	RFre	: 	in std_logic;
	RFr1a	: 	in std_logic_vector(6 downto 0);-- r1 address
	RFr2a	: 	in std_logic_vector(6 downto 0);-- r2 address
	RFr3a	: 	in std_logic_vector(6 downto 0);-- r3 address
	RFr4a	: 	in std_logic_vector(6 downto 0);-- r4 address
--	sent	: 	out std_logic;
	RFr1	: 	out std_logic_vector(127 downto 0);-- data out for r1
	RFr2	:	out std_logic_vector(127 downto 0); -- data out for r2	
	RFr3	: 	out std_logic_vector(127 downto 0);-- data into register
	RFr4	: 	out std_logic_vector(127 downto 0));-- data into register
	
end reg_file;

architecture adderffff of reg_file is		  
type rf_type is array (0 to 127) of std_logic_vector(127 downto 0);
signal tmp_rf: rf_type := (others=> (others=>'0'));
signal reset : std_logic := '0';

begin
	 --sent <= '0';
  	 write1: process(clock, rst, RFwa1, RFwe1, RFw1,tmp_rf)
	 begin
		 if rst ='1'and reset = '0' then
			 tmp_rf(0)(127 downto 64) <= x"0000000000000000";
			 tmp_rf(0)(63 downto 0) <= x"0000000000000000";
			 tmp_rf(1)(127 downto 64) <= x"0000000000000011";
			 tmp_rf(1)(63 downto -0) <= x"0000000000000000";
			 tmp_rf(2) <= x"00000000000001480000000000000000";
			 tmp_rf(3) <= x"000000000001D4560000000000000000";
			 tmp_rf(4) <= x"0000000000FFFFFF0000000000000000";
			 tmp_rf(5) <= x"00000AAAAAA000000000000000000000";
		   	 tmp_rf(6) <= x"00000000123456700000000000000000";
			 tmp_rf(7) <= x"00000111111111000000000000000000";
			 tmp_rf(8) <= x"00023456000000000000000000000000";
			 tmp_rf(9) <= x"00000023400000000000000000000000";
			 tmp_rf(10) <= x"00000000020011000000000000000000";
			 tmp_rf(11) <= x"000023467A0000000000000000000000";
			 tmp_rf(12) <= x"00000000000000000000000000000000";
			 tmp_rf(13) <= x"00000000000000000000000000000000";
			 tmp_rf(14) <= x"00000000000000000000000000000000";
			 tmp_rf(15) <= x"00000000000000000000000000000000";
			 tmp_rf(16) <= x"00000000000000000000000000000000";
			 tmp_rf(17) <= x"00000000000000000000000000000000";
			 tmp_rf(18) <= x"00000000000000000000000000000000";
			 reset <= '1';
    	else
			if (clock'event and clock = '1') then
			  if RFwe1='1' then
			    tmp_rf(conv_integer(RFwa1)) <= RFw1;
			  end if;
			end if;
    	end if;
  	end process;						   
  
  write2: process(clock,rst, RFwa2, RFwe2, RFw2,tmp_rf)
  begin
	  if rst = '0' then
		  if (clock'event and clock = '1') then
			  if RFwe2='1' then
			    tmp_rf(conv_integer(RFwa2)) <= RFw2;
			  end if;
			end if;
	  end if;
  end process;
  
  read1: process(clock, rst, RFre, RFr1a,tmp_rf)
  begin
    if rst='1' then
	RFr1 <= x"00000000000000000000000000000000";
    else
	if (clock'event and clock = '1') then
	  if RFre='1' then								 
	    RFr1 <= tmp_rf(conv_integer(RFr1a));
	--	sent <= '1';
	  end if;
	end if;
    end if;
  end process;
	
  read2: process(clock, rst, RFre, RFr2a,tmp_rf)
  begin
    if rst='1' then
		RFr2<= x"00000000000000000000000000000000";
    else
	if (clock'event and clock = '1') then
	  if RFre='1' then								 
	    RFr2 <= tmp_rf(conv_integer(RFr2a));
	--  	sent <= '1';
	  end if;
	end if;
    end if;
  end process;
  
  read3: process(clock, rst, RFre, RFr3a,tmp_rf)
  begin
    if rst='1' then
		RFr3<= x"00000000000000000000000000000000";
    else
	if (clock'event and clock = '1') then
	  if RFre='1' then								 
	    RFr3 <= tmp_rf(conv_integer(RFr3a));
	 -- 	sent <= '1';
	  end if;
	end if;
    end if;
  end process;
  
  read4: process(clock, rst, RFre, RFr4a,tmp_rf)
  begin
    if rst='1' then
		RFr4<= x"00000000000000000000000000000000";
    else
	if (clock'event and clock = '1') then
	  if RFre='1' then								 
	    RFr4 <= tmp_rf(conv_integer(RFr4a));
	--  	sent <= '1';
	  end if;
	end if;
    end if;
  end process;
end adderffff;
 
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